Round-robin arbiter design and generation

Shin, Eung S.; Mooney, Vincent J.; Riley, George F.

doi:10.1145/581250.581253

Cited by 13 publications

(11 citation statements)

References 2 publications

(2 reference statements)

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“…If there is an available switch path, a grant message is sent to the source port and the allocator opens a unidirectional optical circuit from the source port to the destination port in the case of the baseline scheduler or a bidirectional circuit in the case of proposed scheduler. To deal with contentions, the round-robin method [15] was to ensure fair allocation. As only output port arbitration is required, our previous 45 nm synthesis results show that the allocator can be scaled up to 64 ports while maintaining single cycle allocation with a clock frequency of up to 1.2 GHz [16].…”

Section: Methodsmentioning

confidence: 99%

Low Latency Scheduling Algorithm for Shared Memory Communications over Optical Networks

Madarbux¹,

Laer²,

Watts³

2013

2013 IEEE 21st Annual Symposium on High-Performance Interconnects

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Optical Network on Chips (NoCs) based on silicon photonics have been proposed to reduce latency and power consumption in future chip multi-core processors (CMP). However, high performance CMPs use a shared memory model which generates large numbers of short messages, typically of the order of 8-256B. Messages of this length create high overhead for optical switching systems due to arbitration and switching times. Current schemes only start the arbitration process when the message arrives at the input buffer of the network. In this paper, we propose a scheme which intelligently uses the information from the memory controllers to schedule optical paths. We identified predictable patterns of messages associated with memory operations for a 32 core x86 system using the MESI coherency protocol. We used the first message of each pattern to open the optical paths which will be used by all subsequent messages thereby eliminating arbitration time for the latter. Without considering the initial request message, this scheme can therefore reduce the time of flight of a data message in the network by 29% and that of a control message by 67%. We demonstrate the benefits of this scheduling algorithm for applications in the PARSEC benchmark suite with overall average reductions in overhead latency per message, of 31.8% for the streamcluster benchmark and 70.6% for the swaptions benchmark.

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Section: Methodsmentioning

confidence: 99%

Low Latency Scheduling Algorithm for Shared Memory Communications over Optical Networks

Madarbux¹,

Laer²,

Watts³

2013

2013 IEEE 21st Annual Symposium on High-Performance Interconnects

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“…The arbiter output is connected to the bus. The round robin arbiter in circular mode with equal priority maintains a time slice [1]. Every device connected to the arbiter is provided with a corresponding time slice by means of a circular rotation.…”

Section: A Turn or Tokenmentioning

confidence: 99%

“…There was also port limitation and no RTL schematic shown. Eung S. Shin, Vincent J. Mooney III and George F. Riley proposed a Round Robin Arbiter Generator (RAG) tool [1]. They also concentrated on design procedure.…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable parallel architecture of high speed round robin arbiter

Paul¹,

Khan²,

Rahman³

et al. 2015

2015 International Conference on Electrical, Electronics, Signals, Communication and Optimization (EESCO)

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With a view to managing the increasing traffic in computer networks, round robin arbiter has been proposed to work with packet switching system to have increased speed in providing access and scheduling. Round robin arbiter is a doorway to a particular bus based on request along with equal priority and gives turns to devices connected to it in a cyclic order. Considering the rapid growth in computer networking and the emergence of computer automation which will need much more access to the existing limited resources, this paper emphasizes on designing a reconfigurable round robin arbiter over FPGA which takes parallel requests and processes them with high efficiency and less delay than existing designs. Proposed round robin arbiter encounters with 4 to 12 devices. Results show that with 200% increment in the number of connected devices, only 2.69% increment has been found in the delay. With less delay, proposed round robin arbiter exhibits high speed performance with higher traffic, which is a new feature in comparison with the existing designs.

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“…We consider the arbiter with 4 inputs (shown in Figure 5). First, the priority of inputs is placed in descending order from req[0] to req [3] [25,26]. Thus, req[0] has the highest priority, req [1] has the next priority, and so on.…”

Section: A Hardware Verification Case Of Tmcmentioning

confidence: 99%

Terminal Satisfiability in GSTE

Yang

Chang³

et al. 2014

Journal of Applied Mathematics

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Generalized symbolic trajectory evaluation(GSTE) is an extension of symbolic trajectory evaluation (STE) and a method of model checking. GSTE specifications are given as assertion graphs. There are four efficient methods to verify whether a circuit model obeys an assertion graph in GSTE, Model Checking Strong Satisfiability (SMC), Model Checking Normal Satisfiability (NMC), Model Checking Fair Satisfiability (FMC), and Model Checking Terminal Satisfiability (TMC). SMC, NMC, and FMC have been proved and applied in industry, but TMC has not. This paper gives a six-tuple definition and presents a new algorithm for TMC. Based on these, we prove that our algorithm is sound and complete. It solves the SMC’s limitation (resulting in false negative) without extending from finite specification to infinite specification. At last, a case of using TMC to verify a realistic hardware circuit round-robin arbiter is achieved. Avoiding verifying the undesired paths which are not related to the specifications, TMC makes it possible to reduce the computational complexity, and the experimental results suggest that the time cost by SMC is 3.14× with TMC in the case.

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Round-robin arbiter design and generation

Cited by 13 publications

References 2 publications

Low Latency Scheduling Algorithm for Shared Memory Communications over Optical Networks

Low Latency Scheduling Algorithm for Shared Memory Communications over Optical Networks

Reconfigurable parallel architecture of high speed round robin arbiter

Terminal Satisfiability in GSTE

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