Low Latency Scheduling Algorithm for Shared Memory Communications over Optical Networks

Abstract

Optical Network on Chips (NoCs) based on silicon photonics have been proposed to reduce latency and power consumption in future chip multi-core processors (CMP). However, high performance CMPs use a shared memory model which generates large numbers of short messages, typically of the order of 8-256B. Messages of this length create high overhead for optical switching systems due to arbitration and switching times. Current schemes only start the arbitration process when the message arrives at the input buffer of the network. In this paper, we propose a scheme which intelligently uses the information from the memory controllers to schedule optical paths. We identified predictable patterns of messages associated with memory operations for a 32 core x86 system using the MESI coherency protocol. We used the first message of each pattern to open the optical paths which will be used by all subsequent messages thereby eliminating arbitration time for the latter. Without considering the initial request message, this scheme can therefore reduce the time of flight of a data message in the network by 29% and that of a control message by 67%. We demonstrate the benefits of this scheduling algorithm for applications in the PARSEC benchmark suite with overall average reductions in overhead latency per message, of 31.8% for the streamcluster benchmark and 70.6% for the swaptions benchmark.

Towards zero latency photonic switching in shared memory networks

“…Section 6 will address the issue of the energy consumption of the system. On the question of latency, we showed in that only a very small proportion of individual messages have increased latency because of circuit contention for a NoC. This is because the PARSEC benchmarks, as with other applications, load the network very lightly .…”

“…However, in a shared memory coherence, network messages are communicated on the basis of the cache coherence protocol finite state machine as shown in Figure . For transactions involving just two cores such as the examples in Figure (b), (c) and (d), the memory transaction can be completed by setting up a bidirectional optical path between the two cores . All the information required to set up these bidirectional paths is available in the Miss Status Holding Register at the source port.…”

Reuse Distance Based Circuit Replacement in Silicon Photonic Interconnection Networks for HPC

“…Efforts have been made to explore the use of optical circuits in HPC environments [17,21] or for memory accesses [18][19][20]. However, few of these works consider minimizing setup penalties based on temporal circuit reuse patterns.…”