Reconfigurable parallel architecture of high speed round robin arbiter

Paul, Arnab; Khan, Mamdudul Haque; Rahman, Mostafizur; Khan, Tanvir Zaman; Podder, Prajoy; Khan, Yeasir Akram

doi:10.1109/eesco.2015.7253744

Cited by 2 publications

(1 citation statement)

References 9 publications

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“…We have collected few of them here to provide an insight of the topic. Zheng and Yang (2006) provides two main designs in the form of a parallel round-robin arbiter (PRRA) (Paul et al, 2015) and an improved PRRA (IPRRA). Based on their work, designers suggest that the proposed PRRA design will provide round-robin fairness for all input conditions, whereas their IPRRA is expected to reduce timing parameters over their proposed PRRA.…”

Section: Related Workmentioning

confidence: 99%

Adaptive hybrid arbiter design for real-time traffic-aware scheduling

Khan

Mir

Din

2021

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Purpose This work focused on a basic building block of an allocation unit that carries out the critical job of deciding between the conflicting requests, i.e. an arbiter unit. The purpose of this work is to implement an improved hybrid arbiter while harnessing the basic advantages of a matrix arbiter. Design/methodology/approach The basic approach of the design methodology involves the extraction of traffic information from buffer signals of each port. As the traffic arrives in the buffer of respective ports, information from these buffers acts as a source of differentiation between the ports receiving low traffic rates and ports receiving high traffic rates. A logic circuit is devised that enables an arbiter to dynamically assign priorities to different ports based on the information from buffers. For implementation and verification of the proposed design, a two-stage approach was used. Stage I comprises comparing the proposed arbiter with other arbiters in the literature using Vivado integrated design environment platform. Stage II demonstrates the implementation of the proposed design in Cadence design environment for application-specific integrated chip level implementation. By using such a strategy, this study aims to have a special focus on the feasibility of the design for very large-scale integration implementation. Findings According to the simulation results, the proposed hybrid arbiter maintains the advantage of a basic matrix arbiter and also possesses the additional feature of fault-tolerant traffic awareness. These features for a hybrid arbiter are achieved with a 19% increase in throughput, a 1.5% decrease in delay and a 19% area increase in comparison to a conventional matrix arbiter. Originality/value This paper proposes a traffic-aware mechanism that increases the throughput of an arbiter unit with some area trade-off. The key feature of this hybrid arbiter is that it can assign priorities to the requesting ports based upon the real-time traffic requirements of each port. As a result of this, the arbiter is dynamically able to make arbitration decisions. Now because buffer information is valuable in winning the priority, the presence of a fault-tolerant policy ensures that none of the priority is assigned falsely to a requesting port. By this, wastage of arbitration cycles is avoided and an increase in throughput is also achieved.

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Section: Related Workmentioning

confidence: 99%

Adaptive hybrid arbiter design for real-time traffic-aware scheduling

Khan

Mir

Din

2021

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Árbitros semi-rotatorios con VHDL

Saucedo-Flores,

Galicia-Galicia

2016

Científica

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En los sistemas de buses en un chip (System on-Chip, SoC), las propiedades intelectuales (Intellectual Property, IP) necesitan comunicarse entre cada una para acceder a la funcionalidad requerida. Cuando el bus del SoC es conectado con más IP, la contención ocurre mientras múltiples IP requieren el uso del bus al mismo tiempo. Ello causa que la comunicación entre arquitecturas basadas en un chip bus sea un reto mayor para el diseñador del sistema con las actuales tecnologías SoC. Las arquitecturas de comunicación deben poder adaptarse por sí mismas de acuerdo con los requisitos de tiempo real de las IP. Por ello, los árbitros de buses son propuestos. El árbitro juega un papel importante en el bus de comunicación del SoC. Los máster en un bus de SoC pueden requerir simultáneamente y, por ello, un árbitro es requerido para decidir cuál máster es electo para el acceso del bus. Un árbitro de buses juega un rol vital en el manejo de peticiones desde el maestro y las respuestas del esclavo (como señal ACK, reintento, etc.). El principal objetivo del algoritmo de arbitración es asegurar que solo un maestro tenga acceso al bus en cualquier tiempo dado, los demás maestros son forzados a permanecer ociosos hasta que reciben la concesión de usar el bus.

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Reconfigurable parallel architecture of high speed round robin arbiter

Cited by 2 publications

References 9 publications

Adaptive hybrid arbiter design for real-time traffic-aware scheduling

Adaptive hybrid arbiter design for real-time traffic-aware scheduling

Árbitros semi-rotatorios con VHDL

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