Room Temperature Interconnection Technology for Bonding Fine Pitch Bumps Using NanoWiring, KlettWelding, KlettSintering and KlettGlueing

Roustaie, Farough; Quednau, Sebastian; Dassinger, Florian; Birlem, Olav

doi:10.1109/impact50485.2020.9268570

Cited by 6 publications

(1 citation statement)

References 4 publications

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“…The presented 1 cm 2 -backplane design has been sent to manufacture in 0.18 µm CMOS process within a Multi-Layer Mask run. Furthermore, the resulting wafers will be processed with the KlettWelding technique (12) to transfer the microLED array to the CMOS backplane (Figure 4). Moreover, the future microdisplay will be combined with a microlens array (13) to exchange its versatility as a multipoint light source for scientific applications.…”

Section: Future Workmentioning

confidence: 99%

11‐2: A 9 kfps 1411 PPI GaN‐based µLED Display CMOS Backplane

Canals,

Moro,

Schöttler

et al. 2023

Symp Digest of Tech Papers

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The revolution of the GaN‐on‐Si hybrid integration has redefined microdisplay as a point‐light source for scientific, communication and visualization applications, thanks to their superior capabilities in terms of resolution, brightness and switching speed. In this work, we present a CMOS (Complementary Metal‐Oxide Semiconductor) backplane able to exploit the GaN microarrays capabilities, producing high‐speed patterns (up to 9.15 kfps) at high optical intensities (up to 120 uA per pixel and 16 grey levels) at an unprecedented resolution of 1411 PPI (512×512 pixel with 18um pitch). In addition, the backplane can be operated in pulsed mode, allowing the entire array to be toggled between the stored frame and off state at 1 MHz. Its unique characteristics expand the range of possible applications, from fluorescence‐based performance assays to the manufacturing of DNA chips.

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Section: Future Workmentioning

confidence: 99%

11‐2: A 9 kfps 1411 PPI GaN‐based µLED Display CMOS Backplane

Canals,

Moro,

Schöttler

et al. 2023

Symp Digest of Tech Papers

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Fine-Pitch Copper Nanowire Interconnects for 2.5/3D System Integration

Bickel,

Quednau,

Birlem

et al. 2024

J. Electron. Mater.

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Heterogeneous integration is a key driver within the field of advanced electronic packaging. The realization of tomorrow’s highly integrated electronic systems depends on the combination and compatibility of various integration technologies at the same hierarchy level. The adoption of novel bonding technologies for a cost-effective realization of multi-chiplet systems is a key aspect. Cu nanowire (NW) interconnects exhibit distinct advantages in terms of their scalability down to a few micrometers, the resulting joint properties and moderate demands with respect to the surface preparation, and the cleanliness of the bonding environment. No solder or flux is required for the bonding process, but the NW bumps still can compensate low height differences. The bonding process can be carried out near room temperature under ambient conditions. We demonstrate the technological possibility to integrate the Cu-NWs for a bump processing scheme including the Cu seed etching on 300 mm wafer for the first time. This paper focuses on the microstructure evaluation and the shear test of the formed Cu-NW interconnects fabricated under ambient conditions within a few seconds. The microstructure analysis shows the intact bonded interconnects and reveals high-resolution details of Cu-NWs. The shear strength of the formed interconnects varies between 4.6 MPa and 90.5 MPa depending on the bonding and annealing conditions. Overall, the results of this study highlight the potential of Cu-NW interconnects for future 3D heterogeneous system integration.

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Low-Resistance Room-Temperature Interconnection Technique for Bonding Fine Pitch Bumps

Roustaie

Quednau

Weissenborn

et al. 2021

J. of Materi Eng and Perform

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In this work, we demonstrate on a new interconnection technology which can be used for bonding Flip-Chips with 5-lm-Bumps and fine pitches <5 lm. In this technology, the bumps on both joint partners are coated with metallic nanowires (in most cases copper, in rare cases gold), through an in situ electrochemical deposition process, the so-called NanoWiring process. The diameter of the wires can be adjusted between 30 and 4000 nm, and their length is ranged from 4 to 50 lm. The process is scaled up for 12 inch wafers. The bonding process can be performed directly at wafer level or also at Flip-Chip level. The nanowires overcome the dicing step. The diced chips can be bonded by adjusting and pressing the NanoWired bumps together at room temperature, using the standard bonding devices. The required bonding forces range from 5 to 50 MPa for flip chips, LEDs and sensors. The bonding with nanowires, the so-called KlettWelding, can be explained by diffusion of the nanowires in each other under compression and weaving of the wires as well. The measured shear strength of these connections yields 15-24 MPa. The very large achieved Surface/ Volume quotient of NanoWired surface causes this strength. For a better performance, a prior copper oxide reducing step for the copper NanoWires is needed. This can be done by using standard processes like forming gas plasma or formic acid vapor. By heating during the pressing process up to 230°C, the shear strength increases to 60 MPa. The nanowired interconnections have an electrical conduction in the range of bulk metal, because of their pure metallic nature. Beside microelectronic applications, the bonding of larger metallic plates like aluminium, copper, steel and also flexible polymers, glass, silicon and ceramics are also enabled.

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Room Temperature Interconnection Technology for Bonding Fine Pitch Bumps Using NanoWiring, KlettWelding, KlettSintering and KlettGlueing

Cited by 6 publications

References 4 publications

11‐2: A 9 kfps 1411 PPI GaN‐based µLED Display CMOS Backplane

11‐2: A 9 kfps 1411 PPI GaN‐based µLED Display CMOS Backplane

Fine-Pitch Copper Nanowire Interconnects for 2.5/3D System Integration

Low-Resistance Room-Temperature Interconnection Technique for Bonding Fine Pitch Bumps

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