Fine-Pitch Copper Nanowire Interconnects for 2.5/3D System Integration

Abstract

Heterogeneous integration is a key driver within the field of advanced electronic packaging. The realization of tomorrow’s highly integrated electronic systems depends on the combination and compatibility of various integration technologies at the same hierarchy level. The adoption of novel bonding technologies for a cost-effective realization of multi-chiplet systems is a key aspect. Cu nanowire (NW) interconnects exhibit distinct advantages in terms of their scalability down to a few micrometers, the resulting joint properties and moderate demands with respect to the surface preparation, and the cleanliness of the bonding environment. No solder or flux is required for the bonding process, but the NW bumps still can compensate low height differences. The bonding process can be carried out near room temperature under ambient conditions. We demonstrate the technological possibility to integrate the Cu-NWs for a bump processing scheme including the Cu seed etching on 300 mm wafer for the first time. This paper focuses on the microstructure evaluation and the shear test of the formed Cu-NW interconnects fabricated under ambient conditions within a few seconds. The microstructure analysis shows the intact bonded interconnects and reveals high-resolution details of Cu-NWs. The shear strength of the formed interconnects varies between 4.6 MPa and 90.5 MPa depending on the bonding and annealing conditions. Overall, the results of this study highlight the potential of Cu-NW interconnects for future 3D heterogeneous system integration.