Role of the Potential Barrier in the Electrical Performance of the Graphene/SiC Interface

Abstract

Abstract:In spite of the great expectations for epitaxial graphene (EG) on silicon carbide (SiC) to be used as a next-generation high-performance component in high-power nano-and micro-electronics, there are still many technological challenges and fundamental problems that hinder the full potential of EG/SiC structures and that must be overcome. Among the existing problems, the quality of the graphene/SiC interface is one of the most critical factors that determines the electroactive behavior of this heterostructure. This paper reviews the relevant studies on the carrier transport through the graphene/SiC, discusses qualitatively the possibility of controllable tuning the potential barrier height at the heterointerface and analyses how the buffer layer formation affects the electronic properties of the combined EG/SiC system. The correlation between the sp 2 /sp 3 hybridization ratio at the interface and the barrier height is discussed. We expect that the barrier height modulation will allow realizing a monolithic electronic platform comprising different graphene interfaces including ohmic contact, Schottky contact, gate dielectric, the electrically-active counterpart in p-n junctions and quantum wells.

Atypical quantized resistances in millimeter-scale epitaxial graphene p-n junctions

“…The general properties of the interfacial buffer layer are well-known, with its presence leading to n-type doping in EG. 20,[41][42][43] Recall that E F is the Fermi level of the EG layer, respectively, with E F = ℏv F π n G sign n G .…”

Towards epitaxial graphene p-n junctions as electrically programmable quantum resistance standards

“…One would ideally like to know the range of carrier densities attainable with these gates, and so we first focus on determining the carrier density parameter space in the unipolar case. The well-documented electrical and optical properties of the interfacial buffer layer as well as its interactions with EG allow one to expect inherent n -type doping 25 – 27 . We employ a basic capacitance model to gain an insight into the expected doping.…”

High Voltage Graphene Nanowall Trench MOS Barrier Schottky Diode Characterization for High Temperature Applications

“…The change in ф B value can be explained by Tung's model of barrier inhomogeneity [44]. The barrier inhomogeneity could be due to defects, uneven interface, inhomogeneity in thickness, or presence of insulating patches at the metal-semiconductor interface [35,41,[45][46][47][48]. At low temperature, the electrons do not have sufficient energy to surmount the high barrier, however, due to barrier inhomogeneity, current will flow through an area with lower barrier height.…”