We report on a process for fabricating self-aligned tungsten (W) nanowires with polycrystalline silicon core. Tungsten nanowires as thin as 10 nm were formed by utilizing polysilicon sidewall transfer technology followed by selective deposition of tungsten by chemical vapor deposition (CVD) using WF6 as the precursor. With selective CVD, the process is self-limiting whereby the tungsten formation is confined to the polysilicon regions; hence, the nanowires are formed without the need for lithography or for additional processing. The fabricated tungsten nanowires were observed to be perfectly aligned, showing 100% selectivity to polysilicon and can be made to be electrically isolated from one another. The electrical conductivity of the nanowires was characterized to determine the effect of its physical dimensions. The conductivity for the tungsten nanowires were found to be 40% higher when compared to doped polysilicon nanowires of similar dimensions.

In semiconductor fabrication, there are various methods that can be employed to form fine structures. Such techniques include a combination of advance lithography and etching, chemical mechanical planarization (CMP), or metal lift-off. However, these techniques may not be the easiest or the most cost effective. When using lithographic methods such as ultraviolet (UV), deep ultraviolet (DUV), extended ultraviolet (EUV), E-Beam [1], and X-ray, there are always resolution and alignment issues such as how small a structure can be produced and how closely and accurately a structure can be aligned to another. Even when lithography issues are resolved, patterning of very fine structures is also a problem. Wet chemical etching is not feasible when trying to produce submicrometer features because of large undercuts due to the isotropic nature of the etch solution. Lift-off with sacrificial resist [2] is a more common solution to produce nanostructures, but the technique does have resist imposed limitations where deposition must take place below 200°C because of resist thermal stability preventing its use with chemical vapour deposition processes. Also, organizing nanostructures into highly ordered array can also prove extremely challenging.In this paper, the authors demonstrate a method to produce nanostructures and nanowires with dimensions down to 10nm by a self-alignment process using the standard CMOS spacer technology [3]. In this process, very accurate alignment is achieved because the alignment is not determined by the lithographic tool but by the structures and materials themselves. The spacer technique is commonly used in the fabrication of nanometer transistor and does not require the use of submicron lithographic tools. As illustrated in Figure 1, arrays of polysilicon nanostructures have been fabricated on 8" silicon wafers. These include ultra fine structures down to 20nm with an aspect ratio of 10:1 (Fig. 1b), and 10nm structures with an aspect ratio of 20:1 (Fig 1c). In this process, very accurate alignment is achieved. The formed polysilicon nanostructures can be used as an etch mask to transfer fine patterns to insulating materials such as silicon nitride (Si 3 N 4 ) which in turns is used as a mask for bulk machining of deep silicon structures as shown in Figure 2. The fabricated polysilicon nanowires were phosphorous doped to characterize the effect of length (Fig. 3) and diameter (Fig. 4) on the wire resistance. The resistance of the nanowires was found to increase linearly when varying the wire length from 20 to 500nm where the diameter of the nanowires has a significant impact to the wire resistance when its diameter is less than 50nm.The self-aligned polysilicon nanostructures described in this paper has potential applications in nano-electromechanical devices (NEMS), such as pressure sensors, resistive heaters and capacitive or ohmic beam switches. References[1] G. Rius, J. Liobet, J. Arcamone, X. Borrisé and F. Pérez-Murano, "Electron-and ion-beam lithography for the fabrication of nanomechanical ...

Graphene’s superior electronic and thermal properties have gained extensive attention from research and industrial sectors to study and develop the material for various applications such as in sensors and diodes. In this paper, the characteristics and performance of carbon-based nanostructure applied on a Trench Metal Oxide Semiconductor MOS barrier Schottky (TMBS) diode were investigated for high temperature application. The structure used for this study was silicon substrate with a trench and filled trench with gate oxide and polysilicon gate. A graphene nanowall (GNW) or carbon nanowall (CNW), as a barrier layer, was grown using the plasma enhanced chemical vapor deposition (PECVD) method. The TMBS device was then tested to determine the leakage current at 60 V under various temperature settings and compared against a conventional metal-based TMBS device using TiSi2 as a Schottky barrier layer. Current-voltage (I-V) measurement data were analyzed to obtain the Schottky barrier height, ideality factor, and series resistance (Rs) values. From I-V measurement, leakage current measured at 60 V and at 423 K of the GNW-TMBS and TiSi2-TMBS diodes were 0.0685 mA and above 10 mA, respectively, indicating that the GNW-TMBS diode has high operating temperature advantages. The Schottky barrier height, ideality factor, and series resistance based on dV/dln(J) vs. J for the GNW were calculated to be 0.703 eV, 1.64, and 35 ohm respectively.

We report a method of fabricating an array of high aspect ratio silicon nanochannels which is not dependent on nanolithography techniques and equipment. The method comprises etching of silicon micro-channels in an inductively coupled plasma system (ICP), followed by a thermal oxidation step where silicon is consumed during the process to further shrink the channel to nano dimensions. For the micro-channel formation, silicon dioxide is used as the etch mask during the ICP process where a high etch selectivity of 70:1 between silicon and silicon dioxide was achieved. By thermally oxidizing the etched silicon channels, a uniform array of nanochannels with lateral dimensions down to 40 nm was achieved with significantly high aspect ratio value of at least 65. The grown thermal oxide uniformly covers all surfaces of the silicon nanochannels.

We report on the catalytic growth of multiwalled carbon nanotubes by plasma enhanced chemical vapor deposition using Ni and Co catalyst deposited on SiO2, Si3N 4,ITO and TiN Xbarrier layers; layers which are typically used as diffusive barriers of the catalyst material. Results revealed higher growth rates on conductive ITO and TiN Xas compared to non con-ductiveSiO2, and Si3N 4,barriers. Micrograph images reveal the growth mechanism for nanotubes grown on SiO2, Si3N 4 and ITO to be tip growth while base growth was observed for the TiN X barrier layer. Initial conclusion suggests that conductive diffusion barrier surfaces promotes growth rates however it is possible that multiwalled carbon nanotubes grown onSiO2, and Si3N 4,were encumbered as a result of the formation of silicide as shown in the results here.