Roadmapping RFIC test

Strid, E.W.

doi:10.1109/gaas.1998.722607

Cited by 4 publications

(2 citation statements)

References 2 publications

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“…With regards to the flow charts in Fig. 1, test cost reduction efforts typically fall into three categories [9]: * "Test faster" -increased equipment throughput, operational efficiency (technicians, management, process engineers), ATE test program improvements * "Test earlier" -early identification of faulty devices to prevent incurrence of packaging and additional test cost from further processing * "Test less" -removal of redundant or non-critical tests based on statistical correlations with existing data (i.e. final test vs. wafer test), sampling plan reduction [4,10].…”

Section: Test Philosophy and Economicsmentioning

confidence: 99%

Strategic Test Cost Reduction with On-Chip Measurement Circuitry for RF Transceiver Front-Ends - An Overview

Onabajo

Fernández

Silva-Martínez

et al. 2006

2006 49th IEEE International Midwest Symposium on Circuits and Systems

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This paper addresses key technical and economic issues in the design of on-chip measurement circuitry that can be utilized to reduce the cost of testing. A brief outline is provided for research work related to analog/RF built-in selftest (BIST), on-chip instrumentation, and testing requirements of RF front-end blocks. The overview is intended to present test cost reduction requirements and techniques from a circuit design perspective. One promising approach for the test of fully-integrated RF transceiver front-ends with on-chip loopback and strategically placed power detectors along the RF signal path will be discussed as a demonstrative example of the presented concepts. The main focus in this paper is on reported work that is relevant to improvement of test coverage and cost reduction for on-wafer functional test with minimal area overhead and test time.

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Section: Test Philosophy and Economicsmentioning

confidence: 99%

Strategic Test Cost Reduction with On-Chip Measurement Circuitry for RF Transceiver Front-Ends - An Overview

Onabajo

Fernández

Silva-Martínez

et al. 2006

2006 49th IEEE International Midwest Symposium on Circuits and Systems

View full text Add to dashboard Cite

show abstract

“…Techniques for reducing RFIC test costs can be categorised into those that test less, those that test earlier, and those that test faster [5, 6]. The test‐less technique uses efficient testing methods [7, 8] to eliminate redundant or non‐critical tests based on statistical correlations with the existing measured data and sampling plan reduction.…”

Section: Introductionmentioning

confidence: 99%

Enhancement of radio frequency device's contact test using a novel method

Chen²,

Ko³

2014

IET Science, Measurement & Technology

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This investigation describes novel automatic test equipment for verifying the electric contact of radio frequency (RF) traces between RF devices by, for example, the opens and shorts test. An equivalent circuit for modelling the RF device incorporating RF traces with contact impedance is applied for theoretical analysis of the prototype design. The effectiveness of the proposed novel test methodology is then validated. The measured data from experimental testing of RF devices attained in production runs precisely address the contact issue using the novel methodology presented here.

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A signature test framework for rapid production testing of RF circuits

Voorakaranam¹,

Cherubal²,

Chatterjee³

Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition

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Roadmapping RFIC test

Cited by 4 publications

References 2 publications

Strategic Test Cost Reduction with On-Chip Measurement Circuitry for RF Transceiver Front-Ends - An Overview

Strategic Test Cost Reduction with On-Chip Measurement Circuitry for RF Transceiver Front-Ends - An Overview

Enhancement of radio frequency device's contact test using a novel method

A signature test framework for rapid production testing of RF circuits

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