Strategic Test Cost Reduction with On-Chip Measurement Circuitry for RF Transceiver Front-Ends - An Overview

Abstract

This paper addresses key technical and economic issues in the design of on-chip measurement circuitry that can be utilized to reduce the cost of testing. A brief outline is provided for research work related to analog/RF built-in selftest (BIST), on-chip instrumentation, and testing requirements of RF front-end blocks. The overview is intended to present test cost reduction requirements and techniques from a circuit design perspective. One promising approach for the test of fully-integrated RF transceiver front-ends with on-chip loopback and strategically placed power detectors along the RF signal path will be discussed as a demonstrative example of the presented concepts. The main focus in this paper is on reported work that is relevant to improvement of test coverage and cost reduction for on-wafer functional test with minimal area overhead and test time.

A statistical approach for design and testing of analog circuitry in low-cost SoCs

“…An overview of technical and economic aspects of such approach is found in [1], with a focus on RF front ends.…”

A novel method for RF device's contact test

“…With increasing complexity and Pin-counts on nextgeneration RF devices, the research activities are on demand by incorporating RF technology with massproduction concept for developing a solution, either through low cost means and/or augmenting their installed base with RF functionality [1]- [2]. The IC manufacturing supply chain also possesses a large installed base of production test equipment with limited RF functionality.…”

Enhancement of radio frequency device's contact test using a novel method

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