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In this paper, a novel algorithm has been proposed to measure system specifications of an integrated transmitter, which capture the non-linearities of the system-under-test.The measurement of these specifications is important, as these determine the amount of "interference" created by the transmitting system in adjacent channels while transmitting data in a specific channel. By using an optimized periodic bitstream, with energy concentrated at fewer frequencies, all the specifications of interest are measured. This requires fewer measurements and hence, significantly reduced test time compared to standard test techniques. Studies show that the test time can be reduced considerably by changing the number of periods of the optimum bitsequence without losing accuracy in measurement. The number of test measurements was reduced by a factor of two. Overall, using the proposed approach, more than an order of magnitude reduction in test time was achieved, while the different specifications were measured up to a maximum accuracy of 0.2% of the actual value.

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The execution time of many scientific computing applications is dominated by the time spent in performing sparse matrix vector multiplication (SMV; y A Á x). We consider improving the performance of SMV on multicores by exploiting the dense substructures that are inherently present in many sparse matrices derived from partial differential equation models. First, we identify indistinguishable vertices, i.e., vertices with the same adjacency structure, in a graph representation of the sparse matrix (A) and group them into a supernode. Next, we identify effectively dense blocks within the matrix by grouping rows and columns in each supernode. Finally, by using a suitable data structure for this representation of the matrix, we reduce the number of load operations during SMV while exactly preserving the original sparsity structure of A. In addition, we use ordering techniques to enhance locality in accesses to the vector, x, to yield an SMV kernel that exploits the effectively dense substructures in the matrix. We evaluate our scheme on Intel Nehalem and AMD Shanghai processors. We observe that for larger matrices on the Intel Nehalem processor, our method improves performance on average by 37.35% compared with the traditional compressed sparse row scheme (a blocked compressed form improves performance on average by 30.27%). Benefits of our new format are similar for the AMD processor. More importantly, if we pick for each matrix the best among our method and the blocked compressed scheme, the average performance improvements increase to 40.85%. Additional results indicate that the best performing scheme varies depending on the matrix and the system. We therefore propose an effective density measure that could be used for method selection, thus adding to the variety of options for an auto-tuned optimized SMV kernel that can exploit sparse matrix properties and hardware attributes for high performance.