Ring amplifiers for switched-capacitor circuits

Hershberg,; Weaver,; Sobue,; Takéuchi,; Hamashita,; Moon,

doi:10.1109/isscc.2012.6177090

Cited by 50 publications

(9 citation statements)

References 3 publications

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“…The ADC presented in this paper is designed to serve as a characterization test-bench, and its intentional simplicity leaves much room for improvement. Analog power can be reduced by nearly half of that reported in this work by simply disabling the ring amps when not in use (during the sampling phase), as is detailed in [2]. Additionally, optimization techniques such as stage-scaling and multi-bit MDACs, as well as simply moving to a smaller process, can be used to further improve FoM.…”

Section: Measured Resultsmentioning

confidence: 94%

“…3. Unlike [2], which uses ring amps to assist conventional opamp settling, this design only uses ring amplification, and is fully compatible with process scaling. Due to the lack of common-mode feedback (CMFB), the MDAC employs the float sampling scheme of [3].…”

Section: Power Efficiency and Scalability Featuresmentioning

confidence: 99%

“…Due to the lack of common-mode feedback (CMFB), the MDAC employs the float sampling scheme of [3]. If a fully differential MDAC is desired, the CMFB scheme of [2] can be used.…”

Section: Power Efficiency and Scalability Featuresmentioning

confidence: 99%

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A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers

Hershberg

Weaver

Sobue

et al. 2012

2012 Symposium on VLSI Circuits (VLSIC)

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A ring amplifier based pipelined ADC is presented that uses simple cells constructed from small inverters and capacitors to perform amplification. The basic ring amplifier structure is characterized and demonstrated to be highly scalable, power efficient, and compression-immune (inherent rail-to-rail output swing). The prototype 10.5-bit ADC, fabricated in 0.18µm CMOS technology, achieves 61.5dB SNDR at a 30MHz sampling rate and consumes 2.6mW, resulting in a FoM of 90fJ/conversion-step.Introduction Performing accurate, power efficient amplification in scaled CMOS technologies remains a persistent and pressing challenge. Reduced supply voltages and intrinsic device gains exacerbate the accuracy/power trade-off imposed by the deleterious effects of finite amplifier gain error. Many effective solutions to this problem have been developed -ranging from analog gain-enhancement techniques, digital correction schemes, and even altogether new amplification paradigmsbut the solutions often come with a penalty in the classic speed/power/accuracy tradeoff relationship. Furthermore, the operational paradigm for most amplifier implementations remains based on RC-type settling, which when driving large capacitive loads, benefits little from process scaling (i.e. power-delay product improvements). In other words, most existing approaches to scalable amplification work by masking the symptoms of the disease rather than actually curing it. To cure such a problem, an entirely new amplification paradigm is required -one which is inherently suited to operate in modern and future scaled environments.Ring Amplification This paper explores the concept and practical application of ring amplification. The basic structure of a ring amplifier (alternately: ring amp, RAMP) is shown in Fig. 1, and is the actual transistor-level implementation used in the ADC presented in this paper. The ring amp is effectively a ring oscillator whose input signal takes two separate paths to the output (in fact, for V RP = V RN , it is functionally equivalent to a 3-inverter ring oscillator). When V RP > V RN , the capacitors C 2 and C 3 will embed different voltage offsets in each signal path such that for a certain range of input values, neither M P3 nor M N3 will conduct. As seen in Fig. 2, this non-conduction region, or dead-zone, creates plateaus in the output (and input) waveforms of the amplifier as it oscillates. These plateaus reduce the average gain of the amplifier, and for a sufficiently large dead-zone, the average gain will be reduced enough that the unity-gain frequency now corresponds to a phase shift of less than 180°. When this criterion is met, the oscillator will begin to stabilize and settle. This will occur very quickly (much quicker than the "teaching" example of Fig. 2) due to two key feedback mechanisms which continue to dynamically reduce the effective gain of the ring amplifier (and thus increase phase margin and stability). The first mechanism is due to the fact V IN V OUT V RN Φrst Φrst Φrst V RP 840nm 160nm 840nm 160nm 320nm 160...

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Section: Measured Resultsmentioning

confidence: 94%

Section: Power Efficiency and Scalability Featuresmentioning

confidence: 99%

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A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers

Hershberg

Weaver

Sobue

et al. 2012

2012 Symposium on VLSI Circuits (VLSIC)

Self Cite

View full text Add to dashboard Cite

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“…The total input-referred noise power (N total,in ) in this S/H-less replica driving pipelined ADC is expressed as (7). As the inputreferred noise of the second MDAC (N 2nd_MDAC,in ) is divided by the square of the signal gains ((G 1st_MDAC ) 2 ), the effect of N 2nd_MDAC,in is relatively small compared to N 1st_MDAC,in .…”

Section: Noise Of S/h-less 12-bit 200 Ms/s Replica Driving Pipelined Adcmentioning

confidence: 99%

Noise analysis of replica driving technique and its verification to 12‐bit 200 MS/s pipelined ADC

Lee

Ryu

2019

IET Circuits, Devices & Systems

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This study demonstrates the noise analysis of a replica driving MDAC architecture, which is verified by implementing a 12-bit 200 MS/s replica driving pipelined analogue-to-digital converter (ADC). Based on the noise design strategy with the target effective number of bits = 10.5-bit, the overall dynamic performance degradation by KT/C noise and thermal noise by an amplifier is alleviated by removing the front-end sample-and-hold (S/H) circuit, and the transconductance (g m) of the inner source follower is maximised by increasing the current and threshold voltage (V T) reduction. Replica input sampling networks are designed for the first-stage sub-ADC and the first-stage MDAC with different aspect ratios to minimise the sampling skew for the S/H-less architecture. A prototype 12-bit 200 MS/s ADC is fabricated in a 65 nm complementary metal oxide semiconductor. The measured spurious-free dynamic range (SFDR) and signal-to-noise distortion ratio (SNDR) at a 1.0 MHz input signal is 82.6 and 65.6 dB, respectively, and SFDR and SNDR at the Nyquist (=99.0 MHz) input are 77.3 and 58.6 dB, respectively. The ADC core and the reference driver consume 53.9 and 13.2 mW, respectively, at a 1.2 V supply voltage.

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“…For instance, it requires high gain and high bandwidth opamps in a pipelined ADC to achieve the high accuracy and sampling rate which in turn contributes to significant amount of ADC power budget. To reduce the power, researchers and designers look for some promising power‐efficient techniques that avoid opamp [1–10] and reduce the stringent requirements in the ADC. However, replacing an opamp introduces the non‐linearity, generates the DNL/INL errors and requires a calibration technique to compensate these errors, preferably in digital domain.…”

Section: Introductionmentioning

confidence: 99%

Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology

Singh

Rawat

Agarwal

2017

IET Circuits, Devices & Syst

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A 10-bit pipelined analogue-to-digital converter (ADC) at a sampling rate of 100 MS/s utilising only metal-oxidesemiconductor (MOS) transistors is presented and designed in 1.8 V 0.18 μm standard digital complementary MOS (CMOS) nwell technology. The internal gain of value 2 of the intermediate stages is achieved by using a charge-pump-based concept that avoids the use of power-area inefficient operational amplifier. All the capacitors are realised by capacitors implemented by metal-oxide-semiconductor field-effect transistors (MOSCAPs) that allows easy integration with any inexpensive standard digital CMOS technology, and altogether giving low area-power-cost solution. A low DC gain CMOS differential amplifier in source follower configuration is used and low gain effects are calibrated digitally in the background. Peak differential nonlinearity (DNL) improves from −1/+0.27 least significant bit (LSB) to −0.43/+0.57 LSB and peak integral non-linearity (INL) is reduced from −9.56/+9.3 LSB to within range of ±0.5 LSB after calibration. Also signal-to-noise plus distortion ratio (SNDR) and spurious-free dynamic range (SFDR) increase to 65.4 and 72.08 dB, respectively, after calibration.

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Ring amplifiers for switched-capacitor circuits

Cited by 50 publications

References 3 publications

A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers

A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers

Noise analysis of replica driving technique and its verification to 12‐bit 200 MS/s pipelined ADC

Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology

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