RF Noise Modeling of CMOS 90nm Device Using Enhanced BSIM4 with Additional Noise Source

Shi, Jinglin; Xiong, Yong Zhong; Issaoun, A.; Nan, Lan; Lin, Fujiang; Peng, An-Sam; Cho, M.H.; Chen, D.; Yeh, Chih‐Jung

doi:10.1109/rfit.2007.4443952

Cited by 3 publications

(4 citation statements)

References 10 publications

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“…[6][7][8] Meanwhile, many works addressed on noise modeling of MOSFETs are reported. [9][10][11][12][13] By using the measured Y parameters, Reference [9] reported an extraction method to obtain the noise sources, which can fit the measured results closely. Reference [10] improved V g function by dividing the transistors' channel into two parts and achieved great accuracy at certain frequency points.…”

Section: Introductionmentioning

confidence: 99%

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An improved transistor noise equivalent circuit model for silicon‐on‐insulator transistors considering the frequency dispersion effect

Cao

Liu

2021

Micro & Optical Tech Letters

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Section: Introductionmentioning

confidence: 99%

“…As a result, the model application frequency range is limited. Based on Van der Ziel's noise model, Reference [12] improved BSIM4 by using an external current source to replace the voltage source to represent the induced gate noise. This method can achieve better results up to 18 GHz in comparison to the BSIM4.…”

Section: Introductionmentioning

confidence: 99%

An improved transistor noise equivalent circuit model for silicon‐on‐insulator transistors considering the frequency dispersion effect

Cao

Liu

2021

Micro & Optical Tech Letters

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“…Although HF noise modeling has been widely studied and researched, in most of the published papers, they mainly demonstrated HF noise model fitting at a fixed device size and a few biasing points [1]- [6]. The objective of this paper is to demonstrate scalable HF noise modeling for RFCMOS for a range of geometry sizes, biasing, and frequency points.…”

Section: Introductionmentioning

confidence: 99%

A Scalable RFCMOS Noise Model

Tong

Lim

Yeo

et al. 2009

IEEE Trans. Microwave Theory Techn.

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This paper presents the high-frequency (HF) noise modeling of an RF MOSFET for a 90-nm technology node. A brief discussion on the noise measurement theory is presented to illustrate the limitation of the noise measurement system. The extracted noise sources were studied for their geometry and biasing dependences and by implementing additional noise sources into the small-signal RFCMOS model, accurate HF noise simulation for the transistor can be achieved. Verilog-A is used for the coding of the additional noise sources into the RFCMOS model and the added noise source will compensate the underestimation of the channel thermal noise from the BSIM3v3 core model. Simulated noise circles and the measured noise figures are plotted at other source impedances to show that all the noise parameters are simulated accurately. The biasing and geometry dependences of the measured and simulated noise parameters are presented to demonstrate the scalability of the developed HF noise model. The scalability feature in HF noise model can be implemented into the process design kit (PDK) so that more powerful PDK can be developed for the circuit designers to optimize and simulate their circuit design that requires stringent noise specifications. The accurate noise simulation can ensure better chance of success and reduce the number of tape-out and design cycle time.Index Terms-BSIM3v3, high-frequency (HF) noise model, HF noise modeling, RF MOSFET, RFCMOS, Verilog-A.

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“…By monitoring the trend of the noise sources and implementing them using Verilog-A, accurate and scalable HF noise modeling can be achieved. Furthermore, the scalable HF noise model allows more powerful PDK to be developed so that the optimum device size based on its DC, S-parameters and noise performances can be selected to use in critical RF block such as the low noise amplifier (LNA).Although HF noise modeling has been widely studied and researched, in most of the published papers, they mainly demonstrated HF noise model fitting at a fixed device size and a few biasing points [71],[98]-[102]. The objective of this research is to demonstrate scalable HF noise modeling for RFCMOS transistor for a wide range of geometry sizes, biasing and frequency points.…”

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confidence: 99%

Design of a scalable RF model for deep sub-micron mosfets

Tong¹

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In order to achieve first pass design success and optimized RF circuit design, the process design kit (PDK) provided by the foundry must be equipped with accurate and scalable RF models for circuit simulation and optimization process. However, existing RF MOSFET models provided by most foundries are usually in discrete sizes. This poses many design problems for the integrated circuit (IC) designers because certain transistors' geometry sizes are not available in the PDK. Design optimization is not possible without scalable RFCMOS models and the circuit performance cannot be optimized for a particular technology node used for circuit fabrication. Furthermore, discrete RFCMOS models will limit the design flexibility and increase the difficulty in designing RF circuit blocks to meet more stringent design specifications as the operating frequency increases. Currently in the industry, the RF MOSFET model that was developed is mainly in BSIM3v3 and BSIM4 models. In BSIM3v3, the RF model is developed by macro modeling approach whereby sub-circuit components are added to the core transistor model. In BSIM4, the RF model for the parasitic components were developed and included into the source code of the core model. Therefore, theoretically, there is no need for the addition of the sub-circuit components as in BSIM3v3 RF model. Although these two RF models are able to simulate the transistor's S-parameters, the sub-circuit components used are of discrete values. Thus, scalable RF modeling is still not achieved. Therefore, there is a need to study how to develop a scalable and physical RF MOSFET model. Most of the RF models are developed based on the macro modeling approach. Using this approach, sub-circuit components are added to the transistor's

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RF Noise Modeling of CMOS 90nm Device Using Enhanced BSIM4 with Additional Noise Source

Cited by 3 publications

References 10 publications

An improved transistor noise equivalent circuit model for silicon‐on‐insulator transistors considering the frequency dispersion effect

An improved transistor noise equivalent circuit model for silicon‐on‐insulator transistors considering the frequency dispersion effect

A Scalable RFCMOS Noise Model

Design of a scalable RF model for deep sub-micron mosfets

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