Rethinking Belady's Algorithm to Accommodate Prefetching

Jain, Anshul; Lin, Calvin

doi:10.1109/isca.2018.00020

Cited by 31 publications

(20 citation statements)

References 50 publications

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“…Summary: Hardware cache management is an established difficult problem, which is reflected in the small average speed-ups (usually 1%-5%) achieved by state-of-the-art cache management schemes over the prior best schemes [5,26,28,29,49,52,53]. Our work shows that graph applications present a particularly challenging workload for these schemes, in many cases leading to significant performance slowdowns.…”

Section: A History-based Predictive Schemesmentioning

confidence: 92%

“…These hardware schemes aim to perform two tasks: (1) identify cache blocks that are likely to exhibit high reuse, and (2) protect high reuse cache blocks from cache thrashing. To accomplish the first task, these schemes deploy either probabilistic or prediction-based hardware mechanisms [5,10,13,26,28,29,41,49,51,52,53,57,58,59,60]. However, our work finds that graph-dependent irregular access patterns prevent these schemes from correctly learning which cache blocks to preserve, rendering them deficient for the broad domain of graph analytics.…”

Section: Introductionmentioning

confidence: 96%

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Domain-Specialized Cache Management for Graph Analytics

Faldu

Diamond

Grot

2020

2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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Graph analytics power a range of applications in areas as diverse as finance, networking and business logistics. A common property of graphs used in the domain of graph analytics is a power-law distribution of vertex connectivity, wherein a small number of vertices are responsible for a high fraction of all connections in the graph. These richly-connected, hot, vertices inherently exhibit high reuse. However, this work finds that state-of-the-art hardware cache management schemes struggle in capitalizing on their reuse due to highly irregular access patterns of graph analytics.In response, we propose GRASP, domain-specialized cache management at the last-level cache for graph analytics. GRASP augments existing cache policies to maximize reuse of hot vertices by protecting them against cache thrashing, while maintaining sufficient flexibility to capture the reuse of other vertices as needed. GRASP keeps hardware cost negligible by leveraging lightweight software support to pinpoint hot vertices, thus eliding the need for storage-intensive prediction mechanisms employed by state-of-the-art cache management schemes. On a set of diverse graph-analytic applications with large high-skew graph datasets, GRASP outperforms prior domain-agnostic schemes on all datapoints, yielding an average speed-up of 4.2% (max 9.4%) over the best-performing prior scheme. GRASP remains robust on low-/no-skew datasets, whereas prior schemes consistently cause a slowdown.

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Section: A History-based Predictive Schemesmentioning

confidence: 92%

Section: Introductionmentioning

confidence: 96%

Domain-Specialized Cache Management for Graph Analytics

Faldu

Diamond

Grot

2020

2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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“…However, AOB and ETR are actually general techniques that enable formulating direct-mapped versions of replacement policies, as well as reducing the bandwidth needed to maintain replacement policy state. AOB and ETR can make even state-of-the-art signature-based policies [10,11,12,32,33] suitable for DRAM caches. We show how using Signature-based Hit Predictor (SHiP) [10] as an example.…”

Section: Signature-based Policiesmentioning

confidence: 99%

“…We design a bypassing version of RRIP, RRIP-AOB, and implement ETR on our RRIP-AOB as an example of this class of policies, but our ETR scheme can be easily used to reduce update-cost of other frequency and reuse-based replacement algorithms. Signature-based replacement [10,11,12,32,33] attempt to predict line reuse based on signatures (e.g., PC). We develop a bypassing version of SHiP, called SHiP-AOB, to show how to implement signature-based replacement on caches with low associativity.…”

Section: Replacement / Bypassing Policiesmentioning

confidence: 99%

To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches

Young

Qureshi

2019

2019 IEEE 37th International Conference on Computer Design (ICCD)

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This paper investigates intelligent replacement policies for improving the hit-rate of gigascale DRAM caches. Cache replacement policies are commonly used to improve the hit-rate of on-chip caches. The most effective replacement policies often require the cache to track and update per-line reuse state to inform their decision. A fundamental challenge on DRAM caches, however, is that stateful policies would require significant bandwidth to maintain per-line DRAM cache state. As such, DRAM cache replacement policies have primarily been stateless policies, such as always-install or probabilistic bypass. Unfortunately, we find that stateless policies are often too coarse-grain and become ineffective at the size and associativity of DRAM caches. Ideally, we want a replacement policy that can obtain the hit-rate benefits of stateful replacement policies, but keep the bandwidth-efficiency of stateless policies.We perform our study on a DRAM cache design similar to the one used in Knights Landing, and find that tracking per-line reuse state can enable an effective replacement policy that can mitigate the common thrashing patterns seen in gigascale caches. We propose a stateful replacement/bypass policy called RRIP Age-On-Bypass (RRIP-AOB), that tracks reuse state for high-reuse lines, protects such lines by bypassing other lines, and Ages the state On cache Bypass. Unfortunately, such a stateful technique requires significant bandwidth to update state. To this end, we propose Efficient Tracking of Reuse (ETR). ETR makes state tracking efficient by accurately tracking the state of only one line from a region, and using the state of that line to guide the replacement decisions for other lines in that region. ETR reduces the bandwidth for tracking the replacement state by 70%, and makes stateful policies practical for DRAM caches. Our evaluations with a 2GB DRAM cache, show that our RRIP-AOB and ETR techniques provide 18% speedup while needing less than 1KB of SRAM. DRAM ARRAY DATA (64B)ECC-bits (8B) ROW BUFFERRow Buffer = 32 x (72 byte TAD) AddressData Burst (4 x 18B)

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“…Simulações de memória cache têm seus efeitos alterados pela falta de prefetcher, o que poderia invalidar resultados de vários artigos, inclusive o do próprio ZSim. Com isso, o efeito apresentado em artigos sobre política de substituição de cache seria reduzido, pois o prefetcher já mitiga a latência de acessosà memória principal [Jain and Lin 2018]. Além disso, o efeito da comunicação e a própria ação do prefetch aumentam a contenção nos bancos da cache deúltimo nível.…”

Section: Análise De Comportamento Da Hierarquia De Memóriaunclassified

Impacto do Prefetcher na Precisão de Simulações de Arquiteturas Paralelas

Girelli

Moreira

Serpa

et al. 2019

Anais Do XX Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2019)

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Em arquitetura de computadores, o uso de simuladores é predominante em todos os grupos de pesquisa, com uma ampla variedade de abordagens e implementações.No entanto, falta na literatura uma análise detalhada de simuladores de arquiteturas paralelas que suportem workloads de Computação de Alto Desempenho (High Performance Computing - HPC). Este trabalho busca analisar o impacto do prefetcher na precisão da simulação paralela realizada pelo ZSim, um simulador de arquiteturas paralelas. Observamos que, devido à falta de modelagem de prefetcher, as estatı́sticas da hierarquia de memória apresentam comportamentos imprecisos, com erros de até 2.600%.

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Rethinking Belady's Algorithm to Accommodate Prefetching

Cited by 31 publications

References 50 publications

Domain-Specialized Cache Management for Graph Analytics

Domain-Specialized Cache Management for Graph Analytics

To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches

Impacto do Prefetcher na Precisão de Simulações de Arquiteturas Paralelas

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