Impacto do Prefetcher na Precisão de Simulações de Arquiteturas Paralelas

Girelli, Valéria; Moreira, Francis B.; Serpa, Matheus S.; Navaux, Philippe

doi:10.5753/wscad.2019.8684

Cited by 1 publication

(1 citation statement)

References 13 publications

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“…In a previous work, 4 we performed a first step on understanding the prefetcher behavior over parallel applications and its consequences when simulating with ZSim 5 that does not simulate prefetcher. In this paper, we extend our previous work by: Adding the Sniper 6 simulator—that does support simulation of prefetcher algorithms—in the study; Performing a more detailed analysis of the NPB benchmark performance on real and simulated architecture executions; Performing experiments with the Intel Skylake architecture, which is a more modern architecture, when compared to Intel Sandy Bridge used in the previous study; Adopting the instructions per cycle (IPC) metric to evaluate the performance of the NPB benchmark.…”

Section: Introductionmentioning

confidence: 99%

Investigating memory prefetcher performance over parallel applications: From real to simulated

Girelli

Moreira

Serpa

et al. 2021

Concurrency and Computation

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Memory prefetcher algorithms are widely used in processors to mitigate the performance gap between the processors and the memory subsystem. The complexities behind the architectures and prefetcher algorithms, however, not only hinder the development of accurate architecture simulators, but also hinder understanding the prefetcher's contribution to performance, on both a real hardware and in a simulated environment. In this paper, we contribute to shed light on the memory prefetcher's role in the performance of parallel High‐Performance Computing applications, considering the prefetcher algorithms offered by both the real hardware and the simulators. We performed a careful experimental investigation, executing the NAS parallel benchmark (NPB) on a real Skylake machine, and as well in a simulated environment with the ZSim and Sniper simulators, taking into account the prefetcher algorithms offered by both Skylake and the simulators. Our experimental results show that: (i) prefetching from the L3 to L2 cache presents better performance gains, (ii) the memory contention in the parallel execution constrains the prefetcher's effect, (iii) Skylake's parallel memory contention is poorly simulated by ZSim and Sniper, and (iv) Skylake's noninclusive L3 cache hinders the accurate simulation of NPB with the Sniper's prefetchers.

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