Resource Sharing in Custom Instruction Set Extensions

Abstract

Abstract-Customised processor performance generally increases as additional custom instructions are added. However, performance is not the only metric that modern systems must take into account; die area and energy efficiency are equally important. Resource sharing during synthesis of instruction set extensions (ISEs) can reduce significantly the die area and energy consumption of a customized processor. This may increase the number of custom instructions that can be synthesized with a given area budget. Resource sharing involves combining the graph representations of two or more ISEs which contain a similar sub-graph. This coupling of multiple sub-graphs, if performed naively, can increase the latency of the extension instructions considerably. And yet, as we show in this paper, an appropriate level of resource sharing provides a significantly simpler design with only modest increases in average latency for extension instructions.Based on existing resource-sharing techniques, this study presents a new heuristic that controls the degree of resource sharing between a given set of custom instructions.Our main contributions are the introduction of a parametric method for exploring the trade-offs that can be achieved between instruction latency and implementation complexity, and the coupling of design-space exploration with fast area-delay models for the operators comprising each ISE. We present experimental evidence that our heuristic exposes a broad range of design points, allowing advantageous trade-offs between die area and latency to be found and exploited.

Efficient datapath merging for the overhead reduction of run-time reconfigurable systems

“…On the other hand, resource sharing increases the hardware latency, and we have to consider trade-offs between hardware latencies and the implementation complexity [16]. In general, traditional HLS is not efficient for datapath merging in reconfigurable systems.…”

A high-level synthesis flow for custom instruction set extensions for application-specific processors

“…Most DPM methods begin by computing the WMCS and insert muxes afterwards [1,6,10,18]. Minimizing the area of the muxes inserted for each binary commutative operator is NP-complete, per operator [12].…”

“…Brisk et al [1] and Zuluaga and Topham [18] developed DPM heuristics for DAGs. They decompose each DAG into paths and compute the WMCS via string matching.…”

Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands

“…Brisk, et al proposed a method to share functional units among subgraphs and reduced the hardware area significantly 8) . Zuluaga, et al builds on the work 8) to take clock period constraints into consideration while resource sharing 24) . The previous approaches do not address the important issue of increasing limited data-bandwidth, however, our approach can perform both resource sharing and enhancement of data-bandwidth of custom instructions simultaneously.…”