A high-level synthesis flow for custom instruction set extensions for application-specific processors

Pothineni,; Brisk, Philip; Ienne,; Kumar, Akash; Paul, Paul

doi:10.1109/aspdac.2010.5419795

Cited by 19 publications

(12 citation statements)

References 17 publications

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“…In the literature, most of the multiplexer synthesis techniques require a scheduled graph (Caffarena and Carreras, 2010;Krishnan and Katkoori, 2007;Kim and Liu, 2010;Rim et al, 1992;Huang et al, 1990;Chen and Cong, 2004;Cong and Xu, 2008;Hara-Azumi and Tomiyama, 2012;Pothineni et al, 2010;Kondratyev et al, 2011). Therefore, the results are only "good" for the given schedule.…”

Section: High Level Synthesis For Multiple-wordlength Systems and Mulmentioning

confidence: 97%

A new multi-objective mathematical model for the high-level synthesis of integrated circuits

Aras

Yurdakul

2016

Applied Mathematical Modelling

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Highlights• We develop a biobjective MILP model for HLS design including multiplexer overhead.• Unit selection, operation assignment, scheduling, sharing decisions are made together.• The model is solved exactly to obtain the optimal Pareto frontier.• Including multiplexers improve the solution in terms of minimum latency and area. AbstractAn integrated circuit contains millions of components, all of which have to fit in the reserved silicon area and fulfill a defined functionality within a specified amount of execution time. Therefore, the design of an effective integrated circuit is a nontrivial task. Actually, it can be considered as a multi-objective optimization problem with two conflicting objectives: minimizing the total execution time called latency and the total silicon area of the integrated circuit. The overall problem is composed of tightly-coupled subproblems, i.e., determining the allocation of operators that execute the operations, the assignment of operations to operators, and scheduling of the operations. We formulate a multi-objective mixed-integer linear programming model (MOMILP) to solve this complex problem. It is novel since it incorporates decisions about the so-called multiplexers, which are essential components of an integrated circuit. The proposed MOMILP model is solved exactly using an augmented ε-constrained method. This enables us to find all the Pareto optimal solutions and hence the Pareto frontier for a given problem instance within a reasonable amount of computation time. The minimum latency and minimum area solutions of our model are 13.20% and 7.24% better on the average than the model that ignores multiplexers.

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Section: High Level Synthesis For Multiple-wordlength Systems and Mulmentioning

confidence: 97%

A new multi-objective mathematical model for the high-level synthesis of integrated circuits

Aras

Yurdakul

2016

Applied Mathematical Modelling

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“…ASIPs allow adding new functionality to an extensible baseline ISA in the form of Instruction Set Extensions (ISEs), thereby combining flexibility of a general purpose CPU and performance of an ASIC. The key idea is to analyse the application domain and identify repetitive source code fragments that can be replaced by custom ISE instructions to reduce NCL-EEE-MSD-TR-2012-177, Newcastle University 1 A. Mokhov, A. Iliasov, D. Sokolov, M. Rykunov, A. Yakovlev, A. Romanovsky: Synthesis of Processor Instruction Sets from High-level ISA Specifications overheads associated with the instruction fetch cycle and storage of temporary values [22], as well as to enable additional optimisation opportunities in resource allocation, register binding, and port assignment [15] [34].…”

Section: Introductionmentioning

confidence: 99%

Synthesis of Processor Instruction Sets from High-Level ISA Specifications

Mokhov

Iliasov

Sokolov

et al. 2014

IEEE Trans. Comput.

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As processors continue to get exponentially cheaper for end users following Moore's law, the costs involved in their design keep growing, also at an exponential rate. The reason is ever increasing complexity of processors, which modern EDA tools struggle to keep up with. This paper focuses on the design of Instruction Set Architecture (ISA), a significant part of the whole processor design flow. Optimal design of an instruction set for a particular combination of available hardware resources and software requirements is crucial for building processors with high performance and energy efficiency, and is a challenging task involving a lot of heuristics and high-level design decisions. This paper presents a new compositional approach to formal specification and synthesis of ISAs. The approach is based on a new formalism, called Conditional Partial Order Graphs, capable of capturing common behavioural patterns shared by processor instructions, and therefore providing a very compact and efficient way to represent and manipulate ISAs. The Event-B modelling framework is used as a formal specification and verification back-end to guarantee correctness of ISA specifications.We demonstrate benefits of the presented methodology on several examples, including Intel 8051 microcontroller.

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“…Although few kernels have data dependent control-flow, this approach takes into account the behaviour of both data and instruction cache. Also note that techniques for automatic identification of configurations, as in [25], seem applicable, but we defer investigation of this topic to future work.…”

Section: Re-configurable Fabricmentioning

confidence: 99%

“…Starting with a general-purpose host processor, the idea is to specify an ideally minimal set of (more) special-purpose instructions [25]. By carefully integrating instructions, plus any tightly coupled hardware to support their execution, the goal is more effective implementation of the kernel in question (e.g., with respect to efficiency, memory footprint, or security).…”

Section: Introductionmentioning

confidence: 99%

An Exploration of Mechanisms for Dynamic Cryptographic Instruction Set Extension

Grabher

Großschädl

Hoerder

et al. 2011

Cryptographic Hardware and Embedded Systems – CHES 2011

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Abstract. Instruction Set Extensions (ISEs) supplement a host processor with special-purpose, typically fixed-function hardware components and instructions to utilize them. For cryptographic use-cases, this can be very effective due to the demand for non-standard or niche operations that are not supported by general-purpose architectures. However, one disadvantage of fixed-function ISEs is inflexibility, contradicting a need for "algorithm agility." This paper explores a new approach, namely the provision of re-configurable mechanisms to support dynamic (run-time changeable) ISEs. Our results, obtained using an FPGA-based LEON3 prototype, show that this approach provides a flexible general-purpose platform for cryptographic ISEs with all known advantages of previous work, but relies on careful analysis of the associated security issues.

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A high-level synthesis flow for custom instruction set extensions for application-specific processors

Cited by 19 publications

References 17 publications

A new multi-objective mathematical model for the high-level synthesis of integrated circuits

A new multi-objective mathematical model for the high-level synthesis of integrated circuits

Synthesis of Processor Instruction Sets from High-Level ISA Specifications

An Exploration of Mechanisms for Dynamic Cryptographic Instruction Set Extension

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