Synthesis of Processor Instruction Sets from High-Level ISA Specifications

Abstract

As processors continue to get exponentially cheaper for end users following Moore's law, the costs involved in their design keep growing, also at an exponential rate. The reason is ever increasing complexity of processors, which modern EDA tools struggle to keep up with. This paper focuses on the design of Instruction Set Architecture (ISA), a significant part of the whole processor design flow. Optimal design of an instruction set for a particular combination of available hardware resources and software requirements is crucial for building processors with high performance and energy efficiency, and is a challenging task involving a lot of heuristics and high-level design decisions. This paper presents a new compositional approach to formal specification and synthesis of ISAs. The approach is based on a new formalism, called Conditional Partial Order Graphs, capable of capturing common behavioural patterns shared by processor instructions, and therefore providing a very compact and efficient way to represent and manipulate ISAs. The Event-B modelling framework is used as a formal specification and verification back-end to guarantee correctness of ISA specifications.We demonstrate benefits of the presented methodology on several examples, including Intel 8051 microcontroller.

Building Bridges Between Sets of Partial Orders

“…Comparison of Parameterized Structures. We compare LESs, CPOGs and CLESs on a number of benchmarks coming from the VLSI design domain, in particular, on-chip communication controllers [7] and processor microarchitectures [8]. We observed that a CPOG often has a lower complexity than a corresponding LES, however, the opposite can also be true.…”

“…Table 1 provides a summary of our experimental comparison of the complexity of CPOGs, LESs and CLESs. We compressed different sets of partial orders: phase encoders, decision trees, trees of phase encoders, as well as several sets of processor instructions (from ARM Cortex M0 and Intel 8051 processors [8]).…”

Formal verification of spacecraft control programs (experience report)

“…Although proving properties about the hardware implementation is left for future work, the developed infrastructure provides a way to generate testsuites for the processing core from the formal semantics of REDFIN instructions. Furthermore, one can use the semantics to generate parts of the hardware implementation [20] or synthesise efficient instruction subsets [17].…”

Design of Processors with Reconfigurable Microarchitecture

“…It has been demonstrated that the FSM and PN formalisms are not well-suited to describing families of many related behaviours [8] and the design methodologies based on them have poor scalability in the context of reconfigurable systems. As an appropriate alternative, the Conditional Partial Order Graph model was introduced by Mokhov et al [8,9]. The model was devised to allow implicit description of families of related behaviours in a compact form as will be demonstrated in Sections 3 and 4.…”

“…Once an instruction set is built, it usually undergoes a set of transformations and optimisations which include modification of the set of computational units, changing opcodes of instructions or groups of instructions, modifying the instruction pipeline, etc. Most of these transformations are outside the scope of this work and are defined in [9]. In the following subsections we introduce two new transformaitons.…”