Residual stresses at cavity corners in silicon-on-insulator bonded wafers

Abstract

Uncontrolled residual stresses in both integrated circuit and micro-electro-mechanical system applications may affect device performance and reliability, making microscale experimental analysis of the residual stresses an essential part of process and quality control. This work studies the residual stresses generated from different processing parameters common in the manufacture of silicon-on-insulator wafers with buried cavities (cavity-SOI). The buried cavities can concentrate the residual stresses and generate localized mechanical failures. Infrared photoelasticity and optical profilometry are used here to analyze the stress state in wafers after each of several critical processing steps, each with different process parameters. It is found that the residual stresses associated with cavities in the bonded wafers may significantly increase depending upon the oxidation/etching steps and that the stress magnitude is dependent upon the particular etched cavity geometry. Process-dependent stress states and their generation mechanisms are explained for each processing step. The oxide layer grown on cavity sidewalls is found to significantly impact the residual stress at the cavity corners, with a strong dependence on buried oxide layer thickness. By selecting appropriate processing steps and parameters, the magnitude and orientation of the residual stress in the cavity-SOI wafers can be controlled to enhance reliability.

Quantitative Infrared Photoelasticity of Silicon Photovoltaic Wafers Using a Discrete Dislocation Model

“…The infrared gray field polariscope (IR-GFP) is capable of measuring low optical re tardation associated with thin wafers due to its subfringe resolu tion and allows full-field stress mapping for each silicon wafer in less than 30 s [12]. IR-GFP imaging for residual stress characteri zation is presented in both microelectronic-grade and PV-grade silicon wafers by estimating an analytical wafer stress field [13][14][15], as an alternative to experimentally calibrating the wafer stress state, for example, by cleaving the wafer and measuring the amount of relieved stress [16]. Finite element analysis (FEA) results can be obtained for the stress associated with precipitates in the silicon wafers and compared to the infrared photoelastic measurements.…”

Stress control of plasma enhanced chemical vapor deposited silicon oxide film from tetraethoxysilane

“…In this study, we observed that the slightly tensile stressed or neutral stressed film prepared just by dual-frequency TEOS PECVD becomes 200-300 MPa compressive over time due to water absorption. By annealing at higher temperatures, the residual stress initially becomes more tensile, and then dramatically becomes more compressive once the annealing temperature goes beyond 600 • C. We present a method to prepare stable low tensile stress oxide films by dual-frequency TEOS PECVD and subsequent annealing at temperatures higher than 800 • C. The residual stress of the film can be controlled by the final annealing temperature, which is important for applications that require a stress balanced stack, such as chemical mechanical polishing (CMP) and wafer bonding into SOI (silicon on insulator) wafer [7]. Releasing the low tensile stressed film to a flat membrane without risk of buckling was demonstrated, which is important in many applications that require a flat free-standing membrane [8][9][10][11].…”