Residual stress investigation of via-last through-silicon via by polarized Raman spectroscopy measurement and finite element simulation

Abstract

The residual stresses induced around through-silicon vias (TSVs) by a fabrication process is one of the major concerns of reliability. We proposed a methodology to investigate the residual stress in a via-last TSV. Firstly, radial and axial thermal stresses were measured by polarized Raman spectroscopy. The agreement between the simulated stress level and measured results validated the detail simulation model. Furthermore, the validated simulation model was adopted to the study of residual stress by element death/birth methods. The residual stress at room temperature concentrates at passivation layers owing to the high fabrication process temperatures of 420 °C for SiN film and 350 °C for SiO2 films. For a Si substrate, a high-level stress was observed near potential device locations, which requires attention to address reliability concerns in stress-sensitive devices. This methodology of residual stress analysis can be adopted to investigate the residual stress in other devices.

Shallow trench isolation structure design for through‐silicon vias stress reduction

“…It is found that compared to the TSV filled with copper isolation layer filled with BCB, the TSV filled with the solder core and the p-toluene-HT isolation layer, the thermal stress will be smaller. [10][11][12][13][14] Ye Zhu et al proposed that carbon nanotubes can be used instead of copper as the filling material of TSV, because carbon nanotubes have higher thermal conductivity. 15 Although the replacement of copper with organic materials greatly reduces the thermal stress caused by CTE mismatch, the abovementioned methods are not compatible with the CMOS process and will increase the process cost.…”

“…Wei Feng et al combined the parameterized finite element method (FEM) and polarized Raman spectroscopy in the TSV structure with a ring isolation layer to study the influence of the selection of materials on the thermal stress. It is found that compared to the TSV filled with copper isolation layer filled with BCB, the TSV filled with the solder core and the p‐toluene‐HT isolation layer, the thermal stress will be smaller 10–14 . Ye Zhu et al proposed that carbon nanotubes can be used instead of copper as the filling material of TSV, because carbon nanotubes have higher thermal conductivity 15 .…”

Material effect on thermal stress of annular-trench-isolated through silicon via (TSV)

“…[5][6][7][8][9] Due to the less effective heat spreading in the vertically stacked structure of 3D IC with TSV, thermal issues remain as one of the major reliability concerns. [10][11][12][13] The large differences in coefficient of thermal expansion (CTE) between metal core and Si substrate induce high thermal stresses at the interfaces, causing cracks and defects between the layer and the substrate. [14][15][16] Especially, the thermal stress around device locations in the Si substrate greatly influences the shape, size, and performance of devices.…”