Research of Single-Event Burnout in Power UMOSFETs

Abstract

This brief presents 2-D numerical simulation results of single-event burnout (SEB) in power UMOSFETs (trench-gate MOSFET) and investigates hardening solutions to SEB such as carrier lifetime reduction, emitter doping decrease, and p + plug modification. We find that the linear energy transfer (LET) does not have an important influence on the occurrence of SEB. In addition, we present the effect of a varied ion strike position, and the result is that the position in the middle of the neck is easier to SEB than the other positions. In addition, the single-event gate rupture (SEGR) threshold voltages in different LETs are given in order to compare with SEB. Index Terms-Linear energy transfer (LET), PowerUMOSFET, SEB hardening solution, single-event burnout (SEB).

A Brief Review of Heavy-Ion Radiation Degradation and Failure of Silicon UMOS Power Transistors

“…Wang et al [20] has used commercial TCAD software to simulate SEB in UMOS devices. Figure 6 is a cross section of a half-cell of the structure simulated with physical parameters indicated which approximate a UMOS device with breakdown voltage of 70V and threshold voltage of 3V.…”

“…The UMOS SEB simulations [20] do not explore the results of off perpendicular incident ions. Worst case response may not occur with the incident ion perpendicular to the die surface, but the worst case may be at beam angles almost parallel to the die surface [21].…”

“…They report that the threshold voltages for burnout are markedly increased making the devices less sensitive to SEB when compared to the burnout voltage of the base UMOS structures simulated [20].…”

“…Wang et al [20] simulated SEGR in UMOS devices using the framework developed by Allenspach et al [24,25]. Figure 6 is a cross section of a half-cell of the structure simulated.…”

“…This information allows mapping of bias conditions that allow safe operation or, conversely, device bias conditions that result in SEGR. Figure 8 from [20] displays drain-source voltage that is the threshold for triggering SEGR or SEB in the 70V UMOSFET simulated as a function of incident ion LET. The ion strike is assumed to be incident perpendicular to the die and through the gate material near the center of the trench.…”