2014 Symposium on VLSI Circuits Digest of Technical Papers 2014
DOI: 10.1109/vlsic.2014.6858404
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ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing

Abstract: This study proposes an RC-filtered stress-decoupled (RCSD) 4T2R nonvolatile TCAM (nvTCAM) to 1) suppress match-line (ML) leakage current from match cells (I ML-M ), 2) reduce ML parasitic load (C ML ), 3) decouple NVM-stress from wordlength (WDL) and I ML-MIS . RCSD reduces NVM-stress by 7+x, and achieves a 4+x improvement in speed-WDL-capacity-product. A 128x32b RCSD nvTCAM macro was fabricated using HfO ReRAM and an 180nm CMOS. This paper presents the first ReRAM-based nvTCAM featuring the shortest (1.2ns) s… Show more

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Cited by 16 publications
(5 citation statements)
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“…Thus, to attain fast parallel memory operations, reduced area and low-energy consumption, RRAM-based non-volatile SRAM (nvSRAM) was proposed [174] in which two RRAM cells are stacked on eight transistors, forming an 8T2R structure. Also, nonvolatile ternary content-addressable memory (TCAM) having 4T2R cell structure [175] and non-volatile flip flops having reduced stress time and write power based on RRAM have been demonstrated recently [176].…”
Section: Non-volatile Srammentioning
confidence: 99%
“…Thus, to attain fast parallel memory operations, reduced area and low-energy consumption, RRAM-based non-volatile SRAM (nvSRAM) was proposed [174] in which two RRAM cells are stacked on eight transistors, forming an 8T2R structure. Also, nonvolatile ternary content-addressable memory (TCAM) having 4T2R cell structure [175] and non-volatile flip flops having reduced stress time and write power based on RRAM have been demonstrated recently [176].…”
Section: Non-volatile Srammentioning
confidence: 99%
“…Table 2: DASH-CAM area, power, and latency, compared with HD-CAM [15],EDAM [20] and 1R3T resistive TCAM [10]. Based on timing results of extensive Monte-Carlo simulations, DASH-CAM can be operated at 1GHz.…”
Section: Power Consumption Silicon Area and Speedupmentioning
confidence: 99%
“…DASH-CAM operates at 700 mV and consumes an average of 13.5fJ per 32-cell row. These results are summarized in Table 2, and compared with prior art designs for 𝑘-mer or pattern matching: HD-CAM [15], EDAM [20] and 1R3T resistive TCAM [10]. The main advantage of DASH-CAM over HD-CAM and EDAM is its density, which enables efficient classification of larger genomes, such as bacterial pathogens.…”
Section: Power Consumption Silicon Area and Speedupmentioning
confidence: 99%
“…7(d) shows the circuit of a ReRAM CAM cell [47] consisting of two ReRAMs and two comparison transistors (M1/M2), a write-control transistor (M3), and an ML-driver transistor (M4). The gate and source of the comparison transistor are connected to datalines (DL/DLB) and a dynamic sourceline (DSL), respectively.…”
Section: A Types Of Nano-camsmentioning
confidence: 99%