RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor

Homayoun, Houman; Gupta, Aseem; Veidenbaum, Alexander V.; Sasan, Avesta; Kurdahi, Fadi; Dutt, Nikil

doi:10.1007/978-3-642-11515-8_17

Cited by 11 publications

(5 citation statements)

References 19 publications

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“…Given the results in Figure 1, peripheral circuits are equally if not more important to address in SRAM memories. In addition there is a significant body of work on reducing temperature in processor [1,2,5,23]. Our work considers the effect of temperature on leakage power and we report temperature reduction as well.…”

Section: Circuit-level Leakage Controlmentioning

confidence: 90%

Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units

Homayoun

Sasan

Gupta

et al. 2010

Proceedings of the 7th ACM International Conference on Computing Frontiers

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Leakage currents in on-chip SRAMs: caches, branch predictor, register files and TLBs, are major contributors to the energy dissipated by processors in deep sub-micron technologies. High leakage also increases chip temperature and some SRAM-based structures become thermal hotspots. Previous work has addressed major sources of SRAM leakage in memory cells and bit-lines, making remaining SRAM components, in particular large drivers, the primary source of leakage. This paper proposes an approach to reduce this source of leakage in all major SRAM-based units of the processor, controlling them in a uniform way, yet treating each unit individually based on its behavior and memory organization. The new approach uses multiple bias voltages in sleep transistors allowing a trade-off between leakage reduction and wakeup delay in multi-stage peripheral drivers. Four low-power modes are defined, from basic to ultra low power, and SRAMs dynamically transition between these modes to minimize leakage without sacrificing performance. A novel control mechanism monitors and predicts future processor behavior for mode control. The leakage reduction in individual units is evaluated and shown to vary from 25% for IL1 to 75% for L2 caches. Resulting temperature reduction, including the effect of positive feedback between temperature and leakage power, is evaluated. A significant temperature reduction is achieved in each unit. It is also shown to reduce hot spots in the instruction TLB and branch predictor.

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Section: Circuit-level Leakage Controlmentioning

confidence: 90%

Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units

Homayoun

Sasan

Gupta

et al. 2010

Proceedings of the 7th ACM International Conference on Computing Frontiers

Self Cite

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“…Fig. 5 shows the conventional three ports (i.e., two reads and one write port) SRAM cell used in memory cell of register file [13,15,31,38,6]. The cell is composed of two inverters and three pairs of pass transistors.…”

Section: Modified Register File Structure For Reducing Dynamic Powermentioning

confidence: 99%

Dynamically adaptive register file architecture for energy reduction in embedded processors

Tavana

Khameneh

Goudarzi

2015

Microprocessors and Microsystems

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“…None of these techniques consider the energy consumption on the bus and the decoder for register accesses. Some work [Patel et al 2007;Homayoun et al 2010] try to optimize both power and thermal objectives. They present register relocation mechanisms to redistribute the activity in the register file which take advantage of power gating to shut down the idle banks and reduce temperature of the chip.…”

Section: Related Workmentioning

confidence: 99%

Register allocation for embedded systems to simultaneously reduce energy and temperature on registers

Liu

Orailoğlu

Xue

et al. 2013

ACM Trans. Embed. Comput. Syst.

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Energy and thermal issues are two important concerns for embedded system design. Diminished energy dissipation leads to a longer battery life, while reduced temperature hotspots decelerate the physical failure mechanisms. The instruction fetch logic associated with register access has a significant contribution towards the total energy consumption. Meanwhile, the register file has also been previously shown to exhibit the highest temperature compared to the rest of the components in an embedded processor. Therefore, the optimization of energy and the resolution of the thermal issue for register accesses are of great significance. In this article, register allocation techniques are studied to simultaneously reduce energy consumption and heat buildup on register accesses for embedded systems. Contrary to prevailing intuition, we observe that optimizing energy and optimizing temperature on register accesses conflict with each other. We introduce a rotator hardware in the instruction decoder to facilitate a balanced solution for the two conflicting objectives. Algorithms for register allocation and refinement are proposed based on the access patterns and the effects of the rotator. Experimental results show that the proposed algorithms obtain notable improvements of energy and peak temperature for embedded applications. ACM Reference Format:Liu, T., Orailoglu, A., Xue, C. J., and Li, M. 2013. Register allocation for embedded systems to simultaneously reduce energy and temperature on registers.

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RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor

Cited by 11 publications

References 19 publications

Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units

Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units

Dynamically adaptive register file architecture for energy reduction in embedded processors

Register allocation for embedded systems to simultaneously reduce energy and temperature on registers

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