Reliable adder and multipliers in QCA technology

Raj, Marshal; Lakshminarayanan, G.

doi:10.1088/1361-6641/ac796a

Cited by 5 publications

(3 citation statements)

References 38 publications

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“…To address these troubling issues, a shift from conventional VLSI computing to molecular, DNA, and quantum computing as some viable alternative options might be helpful. The Quantum-dot Cellular Automata (QCA) is one of these intriguing realization technologies that has garnered greater attention recently (9)(10)(11)(12)(13) because of several advantageous qualities. These challenges prompted the solution introduced by Lent in 1997 involving QCA [1].…”

Section: Introductionmentioning

confidence: 99%

“…Multiplication operations find widespread applications in various computational tasks, making them particularly vital. Within processors, multipliers stand as integral components of the arithmetic unit, and their efficiency and speed profoundly impact overall processor performance [10]. The capacity to carry out effective multiplication operations dictates the complexity and speed of processors, so optimizing multipliers is essential to improving the capabilities and efficiency of contemporary processors and digital systems.…”

Section: Introductionmentioning

confidence: 99%

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Quantum-based serial-parallel multiplier circuit using an efficient nano-scale serial adder

2024

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Quantum dot cellular automata (QCA) is one of the newest nanotechnologies. The conventional complementary metal oxide semiconductor (CMOS) technology was superbly replaced by QCA technology. This method uses logic states to identify the positions of individual electrons rather than defining voltage levels. A wide range of optimization factors, including reduced power consumption, quick transitions, and an extraordinarily dense structure, are covered by QCA technology. On the other hand, the serial-parallel multiplier (SPM) circuit is an important circuit by itself, and it is also very important in the design of larger circuits. This paper defines an optimized circuit of SPM circuit using QCA. It can integrate serial and parallel processing benefits altogether to increase efficiency and decrease computation time. Thus, all these mentioned advantages make this multiplier framework a crucial element in numerous applications, including complex arithmetic computations and signal processing. This research presents a new QCA-based SPM circuit to optimize the multiplier circuit's performance and enhance the overall design. The proposed framework is an amalgamation of highly performance architecture with efficient path planning. Other than that, the proposed QCAbased SPM circuit is based on the majority gate and 1-bit serial adder (BSA). BCA circuit has 34 cells and a 0.04 μm 2 area and uses 0.5 clock cycles. The outcomes showed the suggested QCA-based SPM circuit occupies a mere 0.28 µm² area, requires 222 QCA cells, and demonstrates a latency of 1.25 clock cycles. This work contributes to the existing literature on QCA technology, also emphasizing its capabilities in advancing VLSI circuit layout via optimized performance.Ključne besede: množilnik, serijsko-vzporendo, binaren množilnik, nano, komunikacije na osnovi QCA Kvantno vezje zaporedno-paralelnega množilnika z uporabo učinkovitega zaporednega seštevalnika v nano merilu PovzetekKvantni točkovni celični avtomati (QCA) so ena od najnovejših nanotehnologij. Tradicionalno tehnologijo komplementarnih kovinsko oksidnih polprevodnikov (CMOS) je odlično nadomestila tehnologija QCA. Ta metoda uporablja logična stanja za določanje položajev posameznih elektronov in ne definira napetostnih nivojev. Tehnologija QCA pokriva številne optimizacijske dejavnike, vključno z manjšo porabo energije, hitrimi prehodi in izredno gosto strukturo. Po drugi strani pa je vezje serijsko-paralelnega množilnika (SPM) samo po sebi pomembno vezje, zelo pomembno pa je tudi pri načrtovanju večjih vezij. Članek opredeljuje optimizirano vezje SPM z uporabo QCA. V njem lahko združimo prednosti serijske in vzporedne obdelave ter tako povečamo učinkovitost in skrajšamo čas računanja. Zaradi vseh omenjenih prednosti je torej to seštevalno ogrodje ključni element v številnih aplikacijah, vključno s kompleksnimi aritmetičnimi izračuni in obdelavo signalov. V tej raziskavi je predstavljeno novo vezje SPM, ki temelji na QCA, za optimizacijo učinkovitosti vezja množitelja in izboljšanje celotne zasnove. Pred...

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Quantum-based serial-parallel multiplier circuit using an efficient nano-scale serial adder

2024

Informacije MIDEM

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“…Currently, state-of-the-art works include many modules in traditional digital circuits, such as adders [29], multipliers [30,31], dividers [32,33] etc. In 2022, K Raja Sekar et al proposed an array multiplier with a relatively high latency, and also proposed a high-speed serial-parallel multiplier.…”

Section: Introductionmentioning

confidence: 99%

Designs of Array Multipliers with an Optimized Delay in Quantum-Dot Cellular Automata

Yan

Liu

et al. 2023

Electronics

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Quantum-dot cellular automata (QCA) has been considered as a novel nano-electronic technology. With the advantages of low power consumption, high speed, and high integration, QCA has been treated as the potential replacement technology of the CMOS (complementary metal oxide semiconductor) which is currently used in the industry. This paper presents a QCA-based array multiplier with an optimized delay. This type of circuit is the basic building block of many arithmetic logic units and electronic communication systems. Compared to the existing array multipliers, the proposed multipliers have the smallest cell count and area. The proposed designs used a compact clock scheme to reduce the carry delay of the signals. The 2 × 2 array multiplier clock delay was reduced by almost 65% compared to the existing designs. Moreover, since the multiplier exhibits a good scalability, for further proof, we proposed a 3 × 3 array multiplier. Simulation results asserted the feasibility of the proposed multipliers. Extensive comparison results demonstrated that when the design scaling was increased, our proposed designs still displayed an efficient overhead in terms of the delay, cell count, and area. The QCADesigner tool was employed to validate the proposed array multipliers. The QCADesigner-E was used to measure the power dissipation of the alternative compared solutions.

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