Designs of Array Multipliers with an Optimized Delay in Quantum-Dot Cellular Automata

Abstract

Quantum-dot cellular automata (QCA) has been considered as a novel nano-electronic technology. With the advantages of low power consumption, high speed, and high integration, QCA has been treated as the potential replacement technology of the CMOS (complementary metal oxide semiconductor) which is currently used in the industry. This paper presents a QCA-based array multiplier with an optimized delay. This type of circuit is the basic building block of many arithmetic logic units and electronic communication systems. Compared to the existing array multipliers, the proposed multipliers have the smallest cell count and area. The proposed designs used a compact clock scheme to reduce the carry delay of the signals. The 2 × 2 array multiplier clock delay was reduced by almost 65% compared to the existing designs. Moreover, since the multiplier exhibits a good scalability, for further proof, we proposed a 3 × 3 array multiplier. Simulation results asserted the feasibility of the proposed multipliers. Extensive comparison results demonstrated that when the design scaling was increased, our proposed designs still displayed an efficient overhead in terms of the delay, cell count, and area. The QCADesigner tool was employed to validate the proposed array multipliers. The QCADesigner-E was used to measure the power dissipation of the alternative compared solutions.

Optimizing fault tolerance of RAM cell through MUX based modeling and design using symmetries of QCA cells

“…QCA clocking has four clocks, with each clock lagging by a 90º-phase the previous one, as shown in Fig. 2 37 . Every period of a clock has four parts: (1) Switch (2) Hold (3) Release (4) Relax.…”

“…The phase difference allows data transmission through the wire by pipelining 36 .

Figure 2 Clocking in QCA 37 .

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