Reliable 300 mm Wafer Level Hybrid Bonding for 3D Stacked CMOS Image Sensors

Lhostis, S.; Farcy, A.; Deloffre, E.; Lorut, F.; Mermoz, S.; Henrion, Y.; Berthier, Ludovic; Bailly, F.; Scevola, Daniel; Guyader, F.; Gigon, F.; Besset, C.; Pellissier, S.; Gay, L.; Hotellier, N.; Berrigo, Anne-Lise Le; Moreau, S.; Balan, V.; Fournel, Frank; Jouve, A.; Chéramy, S.; Arnoux, M.; Rebhan, Bernhard; Maier, Gerhard; Chitu, L.

doi:10.1109/ectc.2016.202

Cited by 70 publications

(19 citation statements)

References 12 publications

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“…Backside Illuminated SPAD Image Sensor with 7.83µm Pitch in 3D-Stacked CMOS Technology T. Al Abbas 1 , N.A.W. Dutton 2 , O. Almer 1 , S. Pellegrini 2 , Y. Henrion 3 and R.K. Henderson 1 1 School of Engineering, The University of Edinburgh, Edinburgh, UK, email: tarek.alabbas@ed.ac.uk 2 Imaging Division, STMicroelectronics, Edinburgh, UK, 3 STMicroelectronics, Crolles, France…”

Section: Take Down Policymentioning

confidence: 99%

“…The 128×120 prototype has a pixel pitch of 7.83µm making it the smallest pixel reported for SPAD image sensors. A low power, high density 40nm bottom tier hosts the quenching front end and processing electronics while an imaging specific 65nm top tier hosts the photo-detectors with a 1-to-1 hybrid bond connection [1]. The SPAD exhibits a median dark count rate (DCR) below 200cps at room temperature and 1V excess bias, and has a peak photon detection probability (PDP) of 27.5% at 640nm and 3V excess bias.…”

Section: Take Down Policymentioning

confidence: 99%

“…In this work the pixel constituents are split between the two tiers with a 1-to-1 hybrid bond connection [1]. Only the photo-detector is implemented on the top tier to maximize fill factor while the bottom tier contains all the circuitry.…”

Section: Pixelmentioning

confidence: 99%

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Backside illuminated SPAD image sensor with 7.83μm pitch in 3D-stacked CMOS technology

Abbas

Dutton

Almer

et al. 2016

2016 IEEE International Electron Devices Meeting (IEDM)

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Section: Take Down Policymentioning

confidence: 99%

Section: Take Down Policymentioning

confidence: 99%

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Backside illuminated SPAD image sensor with 7.83μm pitch in 3D-stacked CMOS technology

Abbas

Dutton

Almer

et al. 2016

2016 IEEE International Electron Devices Meeting (IEDM)

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“…Nevertheless, some observations are still unaddressed. This paper discusses correlation between EM induced void volumes and time-to-failure (TTF) experimentally observed in the case of hybrid bonding-based test structures for the development of Back-Side Illuminated CMOS Image Sensors (BSI CIS) [5]. For BEoL interconnects, a very few papers have tried to address this topic ( [6] and [7], respectively for Al and single damascene Cu metallizations).…”

Section: Introductionmentioning

confidence: 99%

Correlation Between Electromigration-Related Void Volumes and Time-to-Failure by High Resolution X-Ray Tomography and Modeling

Moreau

Fraczkiewicz

Bouchu

et al. 2019

IEEE Electron Device Lett.

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“…1 Previous studies were reported that 3D integration has already been widely used in CMOS image sensor, NAND flash, etc. [2][3][4][5] 3D integration can be realized by vertical interconnections between the stacked layers using metal bonding techniques. 6 As chip size becomes smaller and I/O density gets higher, there is an urgent desire to develop metal bonding technique suitable for ultra-fine pitch interconnection.…”

Section: Introductionmentioning

confidence: 99%

Low temperature Cu-Cu bonding using copper nanoparticles fabricated by high pressure PVD

Cai

Wang

et al. 2017

AIP Advances

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Copper nanoparticles (Cu NPs) fabricated by physical vapor deposition (PVD) were introduced in Cu-Cu bonding as surface modification. The bonding structure with Ti adhesive/barrier layer and Cu substrate layer was fabricated on both surfaces first. Loose structure with Cu NPs was then deposited by magnetron sputtering in a high pressure environment. Solid state Cu-Cu bonding process was accomplished at 200°C for 3min under the pressure of 20MPa. Die shear test was carried out and an average bonding strength of 36.75MPa was achieved. The analysis of fracture surface revealed a high-reliability bonding structure. According to cross-sectional observations, a void-free intermediate Cu layer with thickness around 10nm was obtained. These results demonstrated that a reliable low temperature time-saving Cu-Cu bonding was realized by Cu NPs between the bonding pairs. This novel bonding method might be one of the most attractive techniques in the application of ultra-fine pitch 3D integration.

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Reliable 300 mm Wafer Level Hybrid Bonding for 3D Stacked CMOS Image Sensors

Cited by 70 publications

References 12 publications

Backside illuminated SPAD image sensor with 7.83μm pitch in 3D-stacked CMOS technology

Backside illuminated SPAD image sensor with 7.83μm pitch in 3D-stacked CMOS technology

Correlation Between Electromigration-Related Void Volumes and Time-to-Failure by High Resolution X-Ray Tomography and Modeling

Low temperature Cu-Cu bonding using copper nanoparticles fabricated by high pressure PVD

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