Reliability Trends with Advanced CMOS Scaling and The Implications for Design

McPherson, J. W.

doi:10.1109/cicc.2007.4405763

Cited by 45 publications

(20 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The vias in the interconnect stack have the highest reliability concerns [23], [24], [25], [26], [27] and incorporating regularity at the lower levels of abstraction shows clear benefits with the UR implementations using the lowest number of vias as is evident from Fig. 2b.…”

Section: A Raw Implementation Metricsmentioning

confidence: 95%

Manufacturable nanometer designs using standard cells with regular layout

Subramaniyan

Larsson-Edefors

2013

International Symposium on Quality Electronic Design (ISQED)

View full text Add to dashboard Cite

Abstract-In addition to performance considerations, designing VLSI circuits at nanometer-scale process technology nodes demands considerations related to manufacturability and cost. Regular layout patterns are known to enhance resilience to random as well as certain types of systematic variations. In this contribution we assess the implications of this layout regularity using design automation for Critical Feature Analysis (CFA) and raw metrics, such as via count. Using the ISCAS'89 benchmark suite, for each benchmark circuit we compare place-and-route implementations that are based on semi-regular and ultra-regular cell layouts. While the CFA counter-intuitively suggests that implementations using ultra-regular layouts have lower Design for Manufacturability (DFM) scores than those using semi-regular layouts, we find that ultra-regular layouts yield implementations with an average of 22% fewer vias at the cost of a small wire length increase.

show abstract

Section: A Raw Implementation Metricsmentioning

confidence: 95%

Manufacturable nanometer designs using standard cells with regular layout

Subramaniyan

Larsson-Edefors

2013

International Symposium on Quality Electronic Design (ISQED)

View full text Add to dashboard Cite

show abstract

“…However, for the finest lines at least, it looks like the direction will be towards sharply higher line resistances as barrier layers and finite size effects become significant [12,13]. Dielectric constants are not likely to go much lower and may actually have to go higher to avoid problems with Time-Dependent Dielectric Breakdown (TDDB) [14,15]. This is also a result of non-scaling behavior, and the high electric fields caused by non-scaled voltages applied across shrinking feature dimensions.…”

Section: Figure 1 Supply Voltage Scaling Breakdownmentioning

confidence: 99%

Circuit design challenges at the 14nm technology node

Warnock¹

2011

Proceedings of the 48th Design Automation Conference

View full text Add to dashboard Cite

Technology scaling non-idealities, already apparent in the transitions between previous technology generations, will become even more pronounced as the world moves from the 22nm node to the 14nm node. Digital logic designers working on highperformance microprocessors and similar projects will face significant new challenges as the basic FET structure is changed in a fundamental way, in order to squeeze more performance from scaled devices. New design constraints and new sources of variability will have to be understood, and new methodologies will be required to enable robust, high-speed designs. In addition, the metal interconnects between devices will also be stressed. Scaled wire RC will likely increase, and new tools and methods will be needed to ensure reliable designs.

show abstract

“…Various reliability issues have worsened to unacceptable levels due to rising power and current densities which increase temperature levels and gradients. Hence, this trend further accelerates the negative impact on long term wear-out effects [1] [2] that are introduced briefly in the following.…”

Section: Introductionmentioning

confidence: 98%

Functional enhancements of TMR for power efficient and error resilient ASIC designs

Sämrow

Cornelius

Gorski

et al. 2011

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

View full text Add to dashboard Cite

Progressive technology scaling raises the need for efficient VLSI design methods facing the increasing vulnerability to permanent physical defects, while considering power efficiency of resulting circuit implementations at the same time. Triple Modular Redundancy (TMR) represents a common method to encounter reliability problems, but has the drawback of increased area and power consumption. This work introduces a Low Power Redundant (LPR) design solution that targets the power penalty of TMR implementations. This is done by enhanced and new functional runtime capabilities for error detection and operation control. By exploiting the inherent modularity and parallelism of TMR, the LPR solution applies additional control logic to switch dynamically between compare phases (to indicate faults and their locations) and parallel operation (with reduced operation frequency). This allows power optimized circuit operation with full support for the treatment of permanent faults. Simulation results on different ALU implementations show a decrease of power consumption of up to 60 % compared to conventional TMR. Furthermore, different strategies for the switching between operation modes are introduced that enable power efficient system operation in the presence of permanent physical defects. Moreover, significant reliability improvements are also achieved due to the adaptive use of the redundant modules.

show abstract

Reliability Trends with Advanced CMOS Scaling and The Implications for Design

Cited by 45 publications

References 17 publications

Manufacturable nanometer designs using standard cells with regular layout

Manufacturable nanometer designs using standard cells with regular layout

Circuit design challenges at the 14nm technology node

Functional enhancements of TMR for power efficient and error resilient ASIC designs

Contact Info

Product

Resources

About