Reliability study on system memories of an iterative MIMO-BICM system

Gimmler-Dumont, Christina; Brehm, Christian; Wehn, Norbert

doi:10.1109/vlsi-soc.2012.7332111

Cited by 8 publications

(14 citation statements)

References 18 publications

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“…Gimmler-Dumont, Brehm, and Wehn studied the effects of hardware errors on the memories of a MIMO-BICM system. 10 Here, we consider voltage variations as an error source that occurs regularly during power-state switching. Although lowering the supply voltage is an effective approach to meet stringent power budgets, it strongly increases the susceptibility to errors in static RAM (SRAM) arrays.…”

Section: Study Of Memory Errorsmentioning

confidence: 99%

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A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience

Kleeberger¹,

Gimmler-Dumont

Weis³

et al. 2013

IEEE Micro

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Section: Study Of Memory Errorsmentioning

confidence: 99%

“…The impact of transient errors in Y_VEC and Y_HAT on the system is almost identical. 10 For low error event rates, the detector can remove the additional hardware noise. For higher error event rates, the communications performance slowly decreases.…”

Section: Study Of Memory Errorsmentioning

confidence: 99%

A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience

Kleeberger¹,

Gimmler-Dumont

Weis³

et al. 2013

IEEE Micro

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“…On algorithm level, the authors propose an increase of iteration number to facilitate resilience against timing errors and soft errors. The same authors also study the resilience of a MIMO-BICM system with iterative receiver and hardware errors that manifest as transient bit errors in various components (Gimmler-Dumont et al, 2012) and conclude that for low error rates, performance of the original system can almost be retained by employing additional iterations.…”

Section: Introductionmentioning

confidence: 99%

Improved fault tolerance of Turbo decoding based on optimized index assignments

Geldmacher

Götze

2014

Adv. Radio Sci.

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Abstract. This paper investigates the impact of an errorprone buffer memory on a channel decoder as employed in modern digital communication systems. On one hand this work is motivated by the fact that energy efficient decoder implementations may not only be achieved by optimizations on algorithmic level, but also by chip-level modifications. One of such modifications is so called aggressive voltage scaling of buffer memories, which, while achieving reduced power consumption, also injects errors into the likelihood values used during the decoding process. On the other hand, it has been recognized that the ongoing increase of integration density with smaller structures makes integrated circuits more sensitive to process variations during manufacturing, and to voltage and temperature variations. This may lead to a paradigm shift from 100 %-reliable operation to fault tolerant signal processing. Both reasons are the motivation to discuss the required co-design of algorithms and underlying circuits. For an error-prone receive buffer of a Turbo decoder the influence of quantizer design and index assignment on the error resilience of the decoding algorithm is discussed. It is shown that a suitable design of both enables a compensation of hardware induced bits errors with rates up to 1 % without increasing the computational complexity of the decoder.

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“…It has been shown in [11] that the errors in the input buffer to the channel preprocessing drastically spoil the receivers' performance even at low error rates, due to propagation to successor blocks. In general, errors lead to mismatch between decomposed channel matrix and received vector, rendering further detection and decoding useless.…”

Section: Introductionmentioning

confidence: 99%

Reliability analysis of MIMO channel preprocessing by fault injection

Tomashevich

Gimmler-Dumont

Wehn

et al. 2014

2014 IEEE International Conference on Wireless for Space and Extreme Environments (WiSEE)

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Reliability of modern MIMO receiver hardware becomes a critical issue due to recent advantages in semiconductor technology and continuous transistor size shrinkage. Most of the research conducted so far, analyzed the impact of solely memory errors on the performance of receivers' individual components (e.g. decoders) and on the system level performance of the whole receiver in terms of Frame Error Rate (FER). This paper presents the first reliability analysis of critical channel preprocessing block of the receiver. The reliability of individual computational submodules of channel preprocessing is assessed by gate level FPGAbased fault injection. The most unreliable sub-module is identified as the boundary cell, yielding the most performance degradation by introducing the FER floor of 10 −3 for SNR value of 10 dB for very low fault injection rate. Within the boundary cell, the inverse square root is identified as least critical.

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Reliability study on system memories of an iterative MIMO-BICM system

Cited by 8 publications

References 18 publications

A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience

A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience

Improved fault tolerance of Turbo decoding based on optimized index assignments

Reliability analysis of MIMO channel preprocessing by fault injection

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