A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience

Kleeberger, Veit B.; Gimmler-Dumont, Christina; Weis, Christian; Herkersdorf, Andreas; Mueller-Gritschneder, Daniel; Nassif, Sani; Schlichtmann, Ulf; Wehn, Norbert

doi:10.1109/mm.2013.67

Cited by 20 publications

(14 citation statements)

References 12 publications

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“…However, to depart from the paradigm of 100% reliable operation, the yield criterion has to be modified; memories with up to a certain number of failures still qualify, as long as the failing bit-cells have no relevant impact on the quality of service of the considered application [8,10,11,18]. As the quality metric and the error tolerance limits vary across applications, this type of yield criterion will have to be set on a per-application basis.…”

Section: Yield Criterion and Impactmentioning

confidence: 99%

“…In this way, significant power reduction can be achieved, and the overhead required for fault tolerance mechanisms can be limited. When designing memories for error-resilient applications, various opportunities for resource saving emerge, such as restricting the use of robust and power hungry bit-cells to protect only the bits that play a more significant role in shaping the output quality [3,[9][10][11]. A recently proposed approach, known as priority-based ECC (P-ECC), limits the overhead by applying ECC only to the higher order bits [4,12].…”

Section: Introductionmentioning

confidence: 99%

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Mitigating the impact of faults in unreliable memories for error-resilient applications

Ganapathy

Karakonstantis

Teman

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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Inherently error-resilient applications in areas such as signal processing, machine learning and data analytics provide opportunities for relaxing reliability requirements, and thereby reducing the overhead incurred by conventional error correction schemes. In this paper, we exploit the tolerable imprecision of such applications by designing an energyefficient fault-mitigation scheme for unreliable data memories to meet target yield. The proposed approach uses a bit-shuffling mechanism to isolate faults into bit locations with lower significance. This skews the bit-error distribution towards the low order bits, substantially limiting the output error magnitude. By controlling the granularity of the shuffling, the proposed technique enables trading-off quality for power, area, and timing overhead. Compared to errorcorrection codes, this can reduce the overhead by as much as 83% in read power, 77% in read access time, and 89% in area, when applied to various data mining applications in 28 nm process technology.

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Section: Yield Criterion and Impactmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Mitigating the impact of faults in unreliable memories for error-resilient applications

Ganapathy

Karakonstantis

Teman

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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“…The error probabilities shown in Fig. 6 can be well approximated for 65 nm by linear or piece-wise linear functions in semi-logarithmic representation [18]: P 6T,cell fail = 10 11.7·V DD /V+5.6 (5)…”

Section: Condiandonal)probability)mentioning

confidence: 99%

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience

Herkersdorf

Aliee

Engel

et al. 2014

Microelectronics Reliability

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The Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro-interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells, voltage variations and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture-level resilience methods. AbstractThe Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells, voltage variations and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture-level resilience methods.

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“…Mitra et al (2005); Yoshimoto et al (2012). However, it has also been recognized (Shanbhag et al, 2010;Mitra et al, 2010;Karakonstantis et al, 2012;Kleeberger et al, 2013), that the development of fault tolerant (error resilient) systems cannot be dealt with in a single perspective, but rather that a crosslayer view is required: A co-design of embedded circuits and signal-processing algorithms will be necessary to efficiently exploit potentials of approaches like AVS and to obtain relatively reliable systems based on unreliable underlying components. This approach constitutes a "paradigm shift from 100 %-reliable operation to fault tolerant signal processing" (Novak et al, 2010).…”

Section: Introductionmentioning

confidence: 99%

Improved fault tolerance of Turbo decoding based on optimized index assignments

Geldmacher

Götze

2014

Adv. Radio Sci.

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Abstract. This paper investigates the impact of an errorprone buffer memory on a channel decoder as employed in modern digital communication systems. On one hand this work is motivated by the fact that energy efficient decoder implementations may not only be achieved by optimizations on algorithmic level, but also by chip-level modifications. One of such modifications is so called aggressive voltage scaling of buffer memories, which, while achieving reduced power consumption, also injects errors into the likelihood values used during the decoding process. On the other hand, it has been recognized that the ongoing increase of integration density with smaller structures makes integrated circuits more sensitive to process variations during manufacturing, and to voltage and temperature variations. This may lead to a paradigm shift from 100 %-reliable operation to fault tolerant signal processing. Both reasons are the motivation to discuss the required co-design of algorithms and underlying circuits. For an error-prone receive buffer of a Turbo decoder the influence of quantizer design and index assignment on the error resilience of the decoding algorithm is discussed. It is shown that a suitable design of both enables a compensation of hardware induced bits errors with rates up to 1 % without increasing the computational complexity of the decoder.

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A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience

Cited by 20 publications

References 12 publications

Mitigating the impact of faults in unreliable memories for error-resilient applications

Mitigating the impact of faults in unreliable memories for error-resilient applications

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience

Improved fault tolerance of Turbo decoding based on optimized index assignments

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