Reliability screening of high-k dielectrics based on voltage ramp stress

Kerber, A.; Pantisano, L.; Veloso, A.; Groeseneken, G.; Kerber, M.

doi:10.1016/j.microrel.2007.01.030

Cited by 81 publications

(26 citation statements)

References 4 publications

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“…It is this voltage we denote as the "disturb voltage (V DIST )", which refers to the minimum voltage needed to trigger the vacancy perturbations in the filament. It is obvious that the V DIST would depend on the RR chosen, analogous to ramp rate dependence of the dielectric breakdown [27] and SET process [28].…”

Section: A Step-stress Rtn Analysismentioning

confidence: 99%

Microscopic origin of random telegraph noise fluctuations in aggressively scaled RRAM and its impact on read disturb variability

Raghavan

Degraeve

Fantini

et al. 2013

2013 IEEE International Reliability Physics Symposium (IRPS)

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Random telegraph noise (RTN) is an importantintrinsic phenomenon of any logic or memory device that is indicative of the reliability and stochastic variability in its performance. In the context of the resistive random access memory (RRAM), RTN becomes a key criterion that determines the read disturb immunity and memory window between the low (LRS) and high resistance states (HRS). With the drive towards ultra-low power memory (low reset current) and aggressive scaling to 10 × 10 nm 2 area, contribution of RTN is significantly enhanced by every trap (vacancy) in the dielectric. The underlying mechanisms governing RTN in RRAM are yet to be fully understood. In this study, we aim to decode the role of conductance fluctuations caused by oxygen vacancy transport and inelastic electron trapping and detrapping processes. The influence of resistance state (LRS, shallow and deep HRS), reset depth and reset stop voltage (V RESET-STOP ) on the conductance variability is also investigated.

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Section: A Step-stress Rtn Analysismentioning

confidence: 99%

Microscopic origin of random telegraph noise fluctuations in aggressively scaled RRAM and its impact on read disturb variability

Raghavan

Degraeve

Fantini

et al. 2013

2013 IEEE International Reliability Physics Symposium (IRPS)

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“…Fig. 4 shows that the area-normalized Weibull distributions of E BD for Hf x Al 1−x O y with k = 14.5 overlap each other, demonstrating a uniform degradation mechanism, i.e., a uniform distribution of weak spots [35], [36]. The inset of Fig.…”

Section: Resultsmentioning

confidence: 89%

Intrinsic Time Zero Dielectric Breakdown Characteristics of HfAlO Alloys

Kim

Jung

et al. 2013

IEEE Trans. Electron Devices

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A thermochemical model describing the relationship between the dielectric breakdown field (E BD ) and dielectric constant(k) of high-k dielectric has been calibrated for Hf x Al 1−x O y alloys with k values from 7 to 24. Metal-insulatormetal (MIM) capacitors with Hf x Al 1−x O y high-k dielectric films were used to extract the intrinsic time zero dielectric breakdown characteristics. Breakdown field values of these Hf x Al 1−x O y alloys were found to decrease as a function of k −0.77 while the electric field acceleration parameter, γ , increases as a function of k 1.37 . Using the thermochemical model calibrated with the experimental data, a Hf x Al 1−x O y 10-year lifetime was extrapolated as a function of the dielectric constant to provide insight for future dielectric development. IndexTerms-Al 2 O 3 , breakdown field, dielectric constant, HfO 2 , lifetime, MIM capacitor, thermochemical model, time-dependent dielectric breakdown (TDDB).

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“…In order to accelerate chip stress and save test time, a ramp voltage stress (RVS) methodology is adopted [28], as depicted in Figure 6. Starting by taking a reference emission at 1.0 V nominal voltage, the supply voltage is later raised to an elevated 1.4 V for 10 minutes (stress #1).…”

Section: Test Setup and Test Conditionsmentioning

confidence: 99%

Counterfeit IC detection using light emission

Song¹,

Stellari²,

Weger³

2014

2014 International Test Conference

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The proliferation of counterfeit Integrated Circuits (ICs) poses a big challenge for the electronics industry as today's supply chain of ICs becomes more complex and expensive. For this reason, it is imperative to mitigate these risks by developing counterfeit IC detection techniques, especially at the chip level. In this paper, a novel counterfeit IC detection method is proposed. It is based on the measurement of intrinsic light emission from CMOS ICs that is a strong function of the device threshold voltage (Vt) for a given technology. In contrast to currently available counterfeit IC detection techniques, the proposed method measures IC degradation after it has been used for a long time and does not require a reference IC to provide a baseline signature. A diff erential technique is used to detect diff erent levels of degradation inside the same chip in order to determine if it is counterfeit. Experimental results presented in this paper show that emission can be effectively used to detect degradation, thus making this technique a very effective wcry to detect counterfeit ICs.

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Reliability screening of high-k dielectrics based on voltage ramp stress

Cited by 81 publications

References 4 publications

Microscopic origin of random telegraph noise fluctuations in aggressively scaled RRAM and its impact on read disturb variability

Microscopic origin of random telegraph noise fluctuations in aggressively scaled RRAM and its impact on read disturb variability

Intrinsic Time Zero Dielectric Breakdown Characteristics of HfAlO Alloys

Counterfeit IC detection using light emission

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