In this study, a 20 cycle atomic layer-deposited (ALD) TiO 2 dielectric interfacial layer was inserted between WS 2 and other metals (Ti and Pd) to lower the Schottky barrier height through a mechanism such as Fermi-level depinning as in a silicon device. In addition to dramatically reducing contact resistance, unipolar transfer characteristics could be achieved in WS 2 FETs by using a TiO 2 dielectric interfacial layer with both low and high work function metal-WS 2 contact systems (Ti-WS 2 and Pd-WS 2 , respectively).Figure 1 a shows the schematic of a back-gate WS 2 FET with a 20 cycle ALD TiO 2 interfacial layer. The channel length and width are ≈3 and ≈20 µm, respectively. A lattice constant of 0.65 nm for the WS 2 was confi rmed as shown in a representative high resolution transmission electron microscopy (HRTEM) image of the metal-TiO 2 -WS 2 stack (Figure 1 b). TiO 2 thickness ≈2.7 nm is expected based on the deposition rate of 0.135 nm per cycle. The fi gure inset is an electron diffraction pattern obtained from a Ti-TiO 2 -WS 2 stack structure. Raman spectra for bi-and multilayer WS 2 are shown in Figure 1 c, and corresponding optical images are shown in Figure 1 d. The Raman spectra for WS 2 include two modes: the E 1 2g mode, which corresponds to the in-plane vibrational motion of atoms, and the A 1g mode, which is attributed to the out-of-plane vibrational motion of atoms. The thickness of the WS 2 layer can be extracted from the shift in the wavenumber. As the thickness increases, the wavenumber between E 1 2g and A 1g and the absolute intensity increase, while the intensity ratio of E 1 2g to A 1g decreases. [ 43 ] Figure 2 a shows the transfer characteristics ( I DS -V BG ) of WS 2 FETs with a Ti electrode (work function ≈4.3 eV). The drain bias was increased from 0.1 to 0.5 V in 0.1 V steps. The transfer characteristics showed bipolar behavior with a hole current for the negative gate bias region and electron current for the positive gate bias region. This is typical behavior for Schottky barrier FETs with a midgap-like contact metal. The effective position of the Fermi level appears to have shifted to the near midgap of WS 2 , forming a high Schottky barrier for both electrons and holes as shown in Figure 2 e. With a metal-semiconductor contact, when the effective workfunction of a metal is shifted by extrinsic mechanisms, the barrier height can be defi ned considering the Fermi-level pinning factor as shown in the equation below 1 B,n 0 gs M s gs 0where B,n 0 Φ is the barrier height, M φ is the work function of the metal electrode, s χ is the electron affi nity of the semiconductor, gs γ is parameter for the gap states, and 0 φ is a charge neutrality position. [ 44 ] The shift in the location of Fermi level can be caused by many factors such as surface states, metal-induced gap states (MIGS), defect states, or disorder-induced gap states, etc. [36][37][38]45,46 ] Recently, 2D transition metal dichalcogenides (TMDs) have attracted intense research interests due to their unique electrical, optica...
Strong demand for power reduction in state-of-the-art semiconductor devices calls for novel devices and architectures. Since ternary logic architecture can perform the same function as binary logic architecture with a much lower device density and higher information density, a switch device suitable for the ternary logic has been pursued for several decades. However, a single device that satisfies all the requirements for ternary logic architecture has not been demonstrated. We demonstrated a ternary graphene field-effect transistor (TGFET), showing three discrete current states in one device. The ternary function was achieved by introducing a metal strip to the middle of graphene channel, which created an N-P-N or P-N-P doping pattern depending on the work function of the metal. In addition, a standard ternary inverter working at room temperature has been achieved by modulating the work function of the metal in a graphene channel. The feasibility of a ternary inverter indicates that a general ternary logic architecture can be realized using complementary TGFETs. This breakthrough will provide a key stepping-stone for an extreme-low-power computing technology.
The operation of chemical vapor-deposited (CVD) graphene field-effect transistors (GFETs) is highly sensitive to environmental factors such as the substrate, polymer residues, ambient condition, and other species adsorbed on the graphene surface due to their high defect density. As a result, CVD GFETs often exhibit a large hysteresis and time-dependent instability. These problems become a major roadblock in the systematic study of graphene devices. We report a facile process to alleviate these problems, which can be used to fabricate stable high performance CVD GFETs with symmetrical current-voltage (I-V) characteristics and an effective carrier mobility over 6000 cm(2) V(-1) s(-1). This process combined a few steps of processes in sequence including pre-annealing in a vacuum, depositing a passivation layer, and the final annealing in a vacuum, and eliminated ∼50% of charging sources primarily originating from water reduction reactions.
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