Reliability problems with VLSI

Fantini, Fausto

doi:10.1016/0026-2714(84)90452-9

Cited by 15 publications

(1 citation statement)

References 130 publications

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“…More data were required to determine failure "mode"; that is, the cause of improper functioning. This work being an integral part of the failure analysis methodology, the conclusions derived from this would be used to establish the failure "mechanism,'' that is the chemical/physical process which led to the failure (Fantini 1984). The metal lid was removed from the 22-pin dual-inline (DIL) ceramic package, exposing the device.…”

Section: Procedures and Resultsmentioning

confidence: 99%

The application of low‐voltage scanning electron microscopy for the analysis of VLSI devices

Woodward

Jones

1989

Scanning

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Section: Procedures and Resultsmentioning

confidence: 99%

The application of low‐voltage scanning electron microscopy for the analysis of VLSI devices

Woodward

Jones

1989

Scanning

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VLSI reliability: Contributions from a three year national research program

Soncini

Canali

Zanoni

et al. 1990

Trans Emerging Tel Tech

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The continuous trend to further I.C. miniaturization implies increased local electric field strength and power dissipation density, and a perverse scaling, behaviour of metal interconnections and contacts. This will result in new failure mechanisms while old ones, non under control, may become a threat again. This work reports on the most relevant results, related to VLSI reliability, obtained by the seven University Research Teams involved in a three years Research Program sponsored by the Italian Ministero Pubblica Istruzione. In particular new methods to investigate electromigration and to localize latch‐up phenomena have been successfully developed. Also test and diagnosis techniques to analyze faults in digital I.C. with emphasis on ECL and custom VLSI have been studied, and electromagnetic interference effects, in operational amplifiers have been modelled and simulated.

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A two‐step methodology for CMOS VLSI reliability improvement: Step one

Davies

Miles

Postoyalko

1988

Quality & Reliability Eng

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Reliability improvement of CMOS VLSI circuits depends on a thorough understanding of the technology, failure mechanisms, and resulting failure modes involved. Failure analysis has identified open circuits, short circuits and MOSFET degradations as the prominent failure modes. Classical methods of fault simulation and test generation are based on the gate level stuck‐at fault model. This model has proved inadequate to model all realistic CMOS failure modes. An approach, which will complement available VLSI design packages, to aid reliability improvement and assurance of CMOS VLSI is outlined. A ‘two‐step’ methodology is adopted. Step one, described in this paper, involves accurate circuit level fault simulation of CMOS cells used in a hierarchical design process. The simulation is achieved using SPICE and pre‐SPICE insertion of faults (PSIF). PSIF is an additional module to SPICE that has been developed and is outlined in detail. Failure modes effects analysis (FMEA) is executed on the SPICE results and FMEA tables are generated. The second step of the methodology uses the FMEA tables to produce a knowledge base. Step two is essential when reliability studies of larger and VLSI circuits are required and will be the subject of a future paper. The knowledge base has the potential to generate fault trees, fault simulate and fault diagnose automatically.

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Reliability problems with VLSI

Cited by 15 publications

References 130 publications

The application of low‐voltage scanning electron microscopy for the analysis of VLSI devices

The application of low‐voltage scanning electron microscopy for the analysis of VLSI devices

VLSI reliability: Contributions from a three year national research program

A two‐step methodology for CMOS VLSI reliability improvement: Step one

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