Reliability challenges for 45nm and beyond

McPherson,

doi:10.1109/dac.2006.229181

Cited by 29 publications

(31 citation statements)

References 6 publications

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“…[1][2][3] With nearly 30+ years of continual CMOS scaling, existing CMOS materials have now been pushed to their physical and reliability limits. Presently, at the 45-65nm nodes, gate oxide thickness is ~ 1.2nm [4] and with a leakage of ~ 100 A/cm 2 at 1.0V [5].…”

Section: Introductionmentioning

confidence: 99%

Reliability Trends with Advanced CMOS Scaling and The Implications for Design

McPherson

2007

2007 IEEE Custom Integrated Circuits Conference

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Scaling (for enhanced performance, increased functionality and cost reduction reasons) has pushed existing CMOS materials much closer to their intrinsic reliability limits. This will require that designers pay very close attention to both front-end-of-line (FEOL) and back-end-of-line (BEOL) reliability issues. As for the FEOL reliability issues, hyperthin gate oxide leakage, time-dependent dielectric breakdown (TDDB), and negative-bias temperature instability (NBTI) are near the top the list. In the case of hyper-thin gate oxides, TDDB can manifest itself in terms of multiple soft-breakdown events thus causing an unwanted rise in leakage; NBTI-induced p-channel device degradation tends to have a significant impact on minimum-voltage circuit operation. As for the important BEOL reliability issues, the top ones are: electromigration (EM), stress migration (SM), low-k dielectric TDDB, and mechanical weaknesses associated with the low-k films and their interfaces. The EM associated with Cu interconnects will continue to worsen with scaling due to increased interface effects; SM will require even fewer vacancies to coalesce which can cause an unwanted via resistance rise; and, relatively poor low-k TDDB behavior and low-k mechanical-weakness issues may require special interconnect layout considerations.

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Section: Introductionmentioning

confidence: 99%

Reliability Trends with Advanced CMOS Scaling and The Implications for Design

McPherson

2007

2007 IEEE Custom Integrated Circuits Conference

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“…For an application consisting of multiple interconnected tasks, the overall reliability and the mean time between failures (MTBF) are given by (8) where N a is the number of tasks and R i (t) is the reliability of task i. The above equation is derived based on the assumption that transient fault occurrences are independent of each other and an application is successful when all tasks of the application executes successfully.…”

Section: A Transient Fault-tolerancementioning

confidence: 99%

“…An area of growing concern in multiprocessor design is concerning error free execution of an application on the platform. Shrinking transistor geometries, growing transistor density and aggressive voltage scaling is negatively impacting the dependability of semiconductor devices by increasing the probability of transient, intermittent and permanent faults [7], [8]. The existing studies on reliability-aware application mapping suffer from the following limitations.…”

Section: Introductionmentioning

confidence: 99%

Aging-aware hardware-software task partitioning for reliable reconfigurable multiprocessor systems

Das

Kumar

Veeravalli

2013

2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)

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Homogeneous multiprocessor systems with reconfigurable area (also known as Reconfigurable Multiprocessor Systems) are emerging as a popular design choice in current and future technology nodes to meet the heterogeneous computing demand of a multitude of applications enabled on these platforms. Application specific mapping decisions on such a platform involve partitioning a given application into software tasks (executed on one or more of the general purpose processors, GPPs) and the hardware tasks (realized as dedicated hardware on the reconfigurable area) to optimize and/or satisfy design constraints such as reliability, performance and design cost. Improving the reliability considering transient faults by increasing the number of checkpoints negatively impacts the reliability considering permanent faults. This trade-off is ignored in all prior studies on task mapping and scheduling. This paper proposes an optimization technique to decide the optimal number of checkpoints for the software tasks which minimizes aging of the GPPs while maximizing the transient fault-tolerance of the overall platform (GPPs and the reconfigurable area) and satisfying design cost and performance. Experiments conducted with synthetic and real-life application task graphs (cyclic and acyclic) demonstrate that the proposed technique minimizes aging and improves the platform lifetime by an average 60% as compared to the existing transient fault-aware techniques. Further, a gradient-based heuristic is proposed to minimize the design space exploration time by upto 500× with less than 5% deviation from optimal solution.

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“…Numerous parasitic and timing effects may show up in the first silicon [4], identifying them is part of silicon debug. With growing circuit complexity and shrinking geometries, the actual behavior of the silicon is hard to model [5], [6], [7] and cannot always be predicted and simulated [8].…”

Section: A Debug and Diagnosismentioning

confidence: 99%

Adaptive Debug and Diagnosis without Fault Dictionaries

Holst¹,

Wunderlich²

2008

2008 13th European Test Symposium

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Diagnosis is essential in modern chip production to increase yield, and debug constitutes a major part in the presilicon development process. For recent process technologies, defect mechanisms are increasingly complex, and continuous efforts are made to model these defects by using sophisticated fault models. Traditional static approaches for debug and diagnosis with a simplified fault model are more and more limited.In this paper, a method is presented, which identifies possible faulty regions in a combinational circuit, based on its input/output behavior and independent of a fault model. The new adaptive, statistical approach combines a flexible and powerful effect-cause pattern analysis algorithm with highresolution ATPG. We show the effectiveness of the approach through experiments with benchmark and industrial circuits.

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Reliability challenges for 45nm and beyond

Cited by 29 publications

References 6 publications

Reliability Trends with Advanced CMOS Scaling and The Implications for Design

Reliability Trends with Advanced CMOS Scaling and The Implications for Design

Aging-aware hardware-software task partitioning for reliable reconfigurable multiprocessor systems

Adaptive Debug and Diagnosis without Fault Dictionaries

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