Reliability and performance of optimised Schmitt trigger gates

Tache, Mihai; Ibrahim, Walid; Kharbash, Fekri; Beiu, Valeriu

doi:10.1049/joe.2018.0091

Cited by 7 publications

(5 citation statements)

References 62 publications

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“…Also in [13], it is proposed a low-power ST by having only one transistor transmitting (at stable output values), considerably reducing power consumption compared with the traditional ST circuit. STs can be optimized by adequate sizing as well as stated in [14] where the optimization of the transistor sizing presented the best metrics for low power applications, in accordance to [15].…”

Section: Process Variability Mitigationmentioning

confidence: 99%

FinFET Inverter Designs: Behavior and Challenges of Process Variability

Moraes

Zimpeck

Minhardt

et al. 2021

JICS

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Abstract— Technology scaling alongside the increasing process variability impact in modern technology nodes are themain reasons to control deviations over metrics in IC nanome-ter designs. Schmitt Triggers are traditionally used for noise immunity enhancement, and have been recently applied to mitigate radiation effects and process variability impact. The main contribution of this work is to trace the relationship between transistor sizing, supply voltage, and process variability to get a low energy consumption circuit while still keeping low levels of deviations due to the impact of process-induced variability. It is shown that a cost-benefit analysis can highlight sets of sizing and supply voltage where it can provide a 37.51% decrease in energy consumption while only increasing its sensibility by 7.42%. Furthermore, it is presented that the dependence of supply voltage and sensibility to process variability is not directly related, with slight decreases in the supply volt-ages bringing better results. Overall, the traditional CMOS inverter is still the fastest and most energy-efficient circuit, although, when comparing noise immunity characteristics, the 6-Transistor Schmitt Trigger presents higher noise margins, slopes, gains, and hysteresis ratios. The improvements,although, may increase propagation times, energy consumption, and area.

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Section: Process Variability Mitigationmentioning

confidence: 99%

FinFET Inverter Designs: Behavior and Challenges of Process Variability

Moraes

Zimpeck

Minhardt

et al. 2021

JICS

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show abstract

“…where γ and 2ϕ F are the body-effect coefficient and surface potential, respectively. Equation (7) declares that by variation of V c1 and V c2 (bulk terminals of M 2a,b ), hysteresis width can be tuned. It should be noted that V c must be smaller than |2ϕ F |+V dd .…”

Section: Proposed Structure Of the Two-stage Schmitt Trigger With Adj...mentioning

confidence: 99%

“…Schmitt triggers can improve the sensitivity of electronic systems to electromagnetic interferences, i.e., they increase the static noise margin of the circuits but at the cost of more power consumption 2 of 12 and delay [5,6]. Accordingly, in general, it is expected that the circuits based on Schmitt triggers operate more reliably in terms of noise immunity [7]. The Schmitt trigger is a bi-stable circuit that is utilized in both analog and digital signal processing systems [8].…”

Section: Introductionmentioning

confidence: 99%

A Sub-Threshold Differential CMOS Schmitt Trigger with Adjustable Hysteresis Based on Body Bias Technique

et al. 2020

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This paper presents a sub-threshold differential CMOS Schmitt trigger with tunable hysteresis, which can be used to enhance the noise immunity of low-power electronic systems. By exploiting the body bias technique to the positive feedback transistors, the hysteresis of the proposed Schmitt trigger is generated, and it can be adjusted by the applied bias voltage to the bulk terminal of the utilized PMOS transistors. The principle of operation and the main formulas of the proposed circuit are discussed. The circuit is designed in a 0.18-μm standard CMOS process with a 0.6 V power supply. Post-layout simulation results show that the hysteresis width of the Schmitt trigger can be adjusted from 45.5 mV to 162 mV where the ratio of the hysteresis width variation to supply voltage is 19.4%. This circuit consumes 10.52 × 7.91 μm2 of silicon area, and its power consumption is only 1.38 µW, which makes it a suitable candidate for low-power applications such as portable electronic, biomedical, and bio-implantable systems.

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“…Low voltage signals and power supplies reduce the noise margins (NM) of the VLSI circuits, making conventional static CMOS logic designs unreliable. Schmitt triggers have significantly higher NMs than static CMOS circuits at low operating voltages, and hence is a far better option for VLSI sensor interface applications 1‐9 . Communication circuits operating under noisy conditions also utilize Schmitt triggers for signal waveform shaping.…”

Section: Introductionmentioning

confidence: 99%

An ultra‐low‐power CNFET‐based improved Schmitt trigger design for VLSI sensor applications

Vidhyadharan

2021

Int J Numerical Modelling

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To enable easy integration of Internet of Things (IoT) sensors with digital very large scale integrtaion (VLSI) circuits, the interface circuits need to operate efficiently even at low power supply voltages, consuming minimum power from the limited onboard supply source. Schmitt triggers have higher noise margins and lower delays as compared to conventional static CMOS logic circuits, at low‐voltage levels and hence are being widely used in VLSI sensor applications. Carbon nanotube FETs (CNFETs) have ION:IOFF and ION:CGG ratios significantly greater than the corresponding CMOS devices, and hence they have been acknowledged as viable candidates to replace CMOS devices in ultra‐low‐power VLSI circuits. This article presents an ultra‐low‐power CNFET‐based Schmitt trigger design, which consumes significantly lower power than the conventional design. The cause of the higher power consumption in conventional CMOS‐based Schmitt trigger is the availability of a direct path between VDD and ground for a longer time duration, during switching. The short‐circuit path in the conventional CMOS Schmitt trigger circuit is the result of the design methodology adopted to obtain hysteresis in VTC curve. The threshold voltage of the CNFET can be easily configured by an appropriate selection of its chiral vector. This property of the CNFET has been used in the implementation of a new, simple but effective Schmitt trigger, which minimizes the short‐circuit currents, while providing the same hysteresis as that of conventional design. The proposed circuit operates at 0.4 V VDD to cater for low‐voltage levels of VLSI sensor applications. The proposed CNFET‐based Schmitt trigger consumes only 0.002 times the power of conventional CMOS Schmitt trigger and operates 56 times faster than the conventional CMOS design. The overall PDP in the proposed CNFET‐based Schmitt trigger has been demonstrated to be merely 0.0003% of the PDP in corresponding conventional designs.

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Reliability and performance of optimised Schmitt trigger gates

Cited by 7 publications

References 62 publications

FinFET Inverter Designs: Behavior and Challenges of Process Variability

FinFET Inverter Designs: Behavior and Challenges of Process Variability

A Sub-Threshold Differential CMOS Schmitt Trigger with Adjustable Hysteresis Based on Body Bias Technique

An ultra‐low‐power CNFET‐based improved Schmitt trigger design for VLSI sensor applications

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