Redundancy techniques for fast static RAMs

Abstract

OVER THE PAST FEW YEARS, there has been a groundswell of support for the use of redundancy in memory components. Redundancy may be the new innovation factor which allows bit density to continue growing at the traditional rate of 2X/year. Previous papers have described redundancy techniques for dynamic RAMS-' and other memory components3 where speed is not the primary goal. This paper will describe techniques utilized in a 40ns 16KX1 static RAM.ent technological factors and random run-to-run process defect distributions. For this 16K static RAM4, area ratios and layout density are such that peripheral circuits such as input and output buffers fail rarely and when they do, are often unrepairable. Thus attention was immediately focused on the failure modes of the memory array and its associated row and column decoders. There are several alternatives for repairing array-associated defects. These methods are best described by stating the group size of the spare repair elements, as shown in Table 1. Spare rows and columns are chosen as the best compromise between modularity and flexibility. Further analysis of the 16K static RAM technology5 indicates that spare rows provide the biggest payoff, since the polysilicon (word line and single bit) design rules are more aggressive than the metal and contact (bit line) design rules.This decision made the circuit design more difficult since the row decoders are in the critical access path whereas the column decoders have much looser speed requirements. As a result, new techniques were developed t o minimize the speed impact of redundancy.Goals for the redundancy circuits are: minimize speed/power impact, minimize added die area, allow convenient programming of fuses at wafer probe, and maximize circuit reliability.The address of a faulty element is programmed into the spare element by electrically blowing polysilicon fuses during wafer probe. The basic circuit block diagram for a spare row is shown Device failure modes are a function of the chip layout, inher-__ bdenum-Polysilicon Technology," ISSCC DIGEST O F TECH-

FPGA Architecture: Survey and Challenges

“…With redundancy, a defective FPGA can be "repaired," and the yield improved, by storing defect information in the device and using that information to adjust the programming of the device to avoid any errors. This has commonly been done in memories [114] and was also proposed for PLAs [207]. These redundant approaches can be classified as either coarse-grained or fine-grained depending on the size of the redundant regions.…”

A signal-conditioning chip for accelerometer applications

“…The popular types of trimming techniques are laser trimming [Brokaw 1996], [Deluca 2002] floating-gate trimming [Sackinger 1988], [Carley 1989], [Tschan 1995], Zener-zap trimming [Price 1965], [Erdi 1975] and fusible link trimming [Schroeder 1977], [Mok 1995], [Kokkonen 1981], [Metzger 1983]. Laser trimming technique has the advantage of trimming component parameters accurately as it applies active trimming (feedback trimming method) in which an output is continually monitored while trimming is performed and stopped as soon as the output reaches a certain level.…”

“…The serial-connection property of the fusible links makes it easy to implement fuse branches that can be blown individually. It is also the reason for popularity of fuse trimming technique in digital implementation [Schroeder 1977], [Kokkonen 1981], [Metzger 1983], [Mok 1995]. However, the major problem is the regrowth of fuse due to electromigration and thermal expansion under environmental temperature effect after the fuse has been blown [Erdi 1975], This gives a problem on reliability of the product.…”