Reduction of hot-carrier generation in 0.1-μm recessed channel nMOSFET with laterally graded channel doping profile

Abstract

To investigate the substrate current characteristics of a recessed channel structure with graded channel doping profile, we have fabricated and simulated the Inverted-Sidewall Recessed-Channel (ISRC) nMOSFET and compared it with a conventional planar nMOSFET. Experimentally, the ISRC nMOSFET shows about 30% reduction of substrate current, even though the drain current is almost the same. At 0.12-m channel length, the ISUB=IDS value of the conventional nMOSFET is measured to be 1.68 times higher than that of the ISRC nMOSFET. Also, using simulation, it is verified that the reduction of electric field at the drain junction of ISRC nMOSFET results from the graded channel doping profile, not from the recessed channel structure.

Operation and scalability of dopant-segregated Schottky barrier MOSFETs with recessed channels

“…As the scale of MOSFETs approaches the sub-100 nm regimes of devices, the short-channel effect has been controlled by introducing RC architecture in practical CMOS technologies [14][15][16][17][18]. Because of their excellent short-channel immunity and off-leakage suppression, RC-type MOSFETs have been used as the array access transistors in the sub-90 nm DRAM technologies [19][20][21][22][23].…”

Parasitic capacitance characteristics of deep submicrometre grooved gate MOSFETs

“…The reasons for the superiority of grooved gate devices over conventional planar devices in suppressing short channel effects, such as the lowering of threshold voltage with shorter channel lengths and improved hot carrier reliability, have been discussed earlier [1][2][3][4][5][6]. The merits of other related device structures, such as recessed channel MOSFETs [7][8][9] and partially raised source/drain (SD) structures [10,11], have also been investigated for channel lengths in the deep submicrometre regime.…”

“…Many techniques such as tilted SD implant have been suggested to control the length and doping profile of this region to enhance device performance [16,17]. Furthermore, many of the other non-conventional device structures, such as recessed channel [7][8][9], raised SD [10,11], fully overlapped nitride etch defined (FOND) [18] and gate-drain overlapped device (GOLD) [19] structures, feature a longer gate-to-SD overlap region to aid the suppression of short channel and hot carrier effects. Extrinsic capacitance models, which are based on approximate doping profiles and simplified expressions for accumulated lengths of this region, such as that given in [20], may prove to be too inaccurate for their analysis.…”