Reducing structural bias in technology mapping

Chatterjee, Saurav; Mishchenko, Alan; Brayton, Robert K.; Wang, X.; Kam, Timothy

doi:10.1109/iccad.2005.1560122

Cited by 51 publications

(26 citation statements)

References 17 publications

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“…It can be applied to both a Boolean network and a set of structural choices derived for the Boolean network. -choice [Chatterjee et al 2005] is a logic synthesis script to derive structural choices. It performs 15 passes of AIG rewriting [Mishchenko et al 2006b] and collects three AIG snapshots of the network: the original one, the final one, and the intermediate one saved after the first 5 rewriting passes.…”

Section: The Proposed Algorithm Was Implemented In Abc [Berkeley 2007mentioning

confidence: 99%

“…The quality of FPGA mapping (both delay and area) is often substantially improved after performing several iterations of Mapping with Structural Choices (MSC), as presented in Lehman et al [1997] and Chatterjee et al [2005]. In our experiments, MSC reduced LUTs, logic levels, and edges by · 14: 3 9.1%, 7.9%, and 8.1%, respectively, compared to the same mapping without structural choices on academic benchmarks.…”

Section: Introductionmentioning

confidence: 95%

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WireMap

Jang

Chan

Chung

et al. 2009

ACM Trans. Reconfigurable Technol. Syst.

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This article presents a new technology mapper, WireMap. The mapper uses an edge flow heuristic to improve the routability of a mapped design. The heuristic is applied during the iterative mapping optimization to reduce the total number of pin-to-pin connections (or edges). On academic benchmark (ISCAS, MCNC, and ITC designs), the average edge reduction of 9.3% is achieved while maintaining depth and LUT count compared to state-of-the-art technology mapping. Placing and routing the resulting netlists leads to an 8.5% reduction in the total wirelength, a 6.0% reduction in minimum channel width, and a 2.3% reduction in critical path delay. This technique is applied in the Xilinx ISE Design tool to evaluate its effect on industrial Virtex5 circuits. In a set of 20 large designs, we find the edge reduction is 6.8% while total wirelength measured in the placer is reduced by 3.6%. Applying WireMap has an additional advantage of reducing an average number of inputs of LUTs without increasing the total LUT count and depth. The percentages of 5-and 6-LUTs in a typical design are reduced, while the percentages of 2-, 3-, and 4-LUTs are increased. These smaller LUTs can be merged into pairs and implemented using the dual-output LUT structure found in commercial FPGAs. For academic benchmarks, WireMap leads to 9.4% fewer dual-output LUTs after merging. For the industrial designs, WireMap leads to 6.3% fewer dual-output Virtex5 LUTs.

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Section: The Proposed Algorithm Was Implemented In Abc [Berkeley 2007mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 95%

WireMap

Jang

Chan

Chung

et al. 2009

ACM Trans. Reconfigurable Technol. Syst.

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“…Other applications of factor cuts would be to improve the quality of standard cell mapping [4] and of logic synthesis using re-writing [10]. The cut size correlates with the capability of a mapper (or re-writing algorithm) to overcome structural bias.…”

Section: Introductionmentioning

confidence: 99%

“…In this application factor cuts are used heuristically to improve the quality of the mapping obtained, over that of simple mapping which does not fully exploit macrocells. In this framework, factor cuts may be seen as an efficient method of reducing structural bias [4], by allowing deeper matches that match the macrocell as a whole, instead of breaking it into its constituent parts.…”

Section: Introductionmentioning

confidence: 99%

Factor cuts

Chatterjee

Mishchenko

Brayton

2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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Enumeration of bounded size cuts is an important step in several logic synthesis algorithms such as technology mapping and re-writing. The standard algorithm does not scale beyond 6 or 7 inputs because it enumerates all cuts and there are too many of them. We address the enumeration problem by introducing the notion of cut factorization. In cut factorization, one enumerates global and local cuts (collectively called the factor cuts) of the network, and uses these to generate other cuts. Depending on how global and local cuts are defined, one obtains different factorization schemes. In the first scheme, complete factorization, it is possible to generate any cut from factor cuts. However, complete factorization is expensive though less expensive than exhaustive enumeration. In the second scheme, partial factorization, there is no guarantee of generating all cuts from factor cuts. However, it is much faster, and produces good results. In this paper we also present two applications of factor cuts: LUT mapping and macrocell mapping. In LUT mapping, we find that considering only factor cuts guarantees depth optimality for most nodes in the network. For the remaining nodes, other cuts need to be generated from factor cuts and examined. In macrocell mapping, we focus on a particular 9-input macrocell, and use factor cuts as a heuristic method to improve depth by reducing structural bias. Factor cuts are used to map the macrocell as a whole whenever possible instead of mapping its parts separately. In this context factor cuts enable a new quality-run-time tradeoff between mapping parts of the macrocell separately (poor quality), and mapping using all 9-input cuts (long run-time).

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“…In synthesis, technology independent optimizations are used before technology mapping, and there is a strong correlation between circuit sizes before and after mapping [2]. In this work we propose a method to minimize the number of nodes in the and-inverter graph (AIG) representation of a technology independent sequential design.…”

Section: Introductionmentioning

confidence: 99%

Merging nodes under sequential observability

Case¹,

Кравец

Mishchenko

et al. 2008

Proceedings of the 45th Annual Design Automation Conference

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This paper presents a new type of sequential technology independent synthesis. Building on the previous notions of combinational observability and sequential equivalence, sequential observability is introduced and discussed. By considering both the sequential nature of the design and observability simultaneously, better results can be obtained than with either algorithm alone. The experimental results show that this method can reduce the technology-independent gate count up to 10% more than the previously best known synthesis techniques.

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Reducing structural bias in technology mapping

Cited by 51 publications

References 17 publications

WireMap

WireMap

Factor cuts

Merging nodes under sequential observability

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