WireMap

Abstract

This article presents a new technology mapper, WireMap. The mapper uses an edge flow heuristic to improve the routability of a mapped design. The heuristic is applied during the iterative mapping optimization to reduce the total number of pin-to-pin connections (or edges). On academic benchmark (ISCAS, MCNC, and ITC designs), the average edge reduction of 9.3% is achieved while maintaining depth and LUT count compared to state-of-the-art technology mapping. Placing and routing the resulting netlists leads to an 8.5% reduction in the total wirelength, a 6.0% reduction in minimum channel width, and a 2.3% reduction in critical path delay. This technique is applied in the Xilinx ISE Design tool to evaluate its effect on industrial Virtex5 circuits. In a set of 20 large designs, we find the edge reduction is 6.8% while total wirelength measured in the placer is reduced by 3.6%. Applying WireMap has an additional advantage of reducing an average number of inputs of LUTs without increasing the total LUT count and depth. The percentages of 5-and 6-LUTs in a typical design are reduced, while the percentages of 2-, 3-, and 4-LUTs are increased. These smaller LUTs can be merged into pairs and implemented using the dual-output LUT structure found in commercial FPGAs. For academic benchmarks, WireMap leads to 9.4% fewer dual-output LUTs after merging. For the industrial designs, WireMap leads to 6.3% fewer dual-output Virtex5 LUTs.

Bulletin of the Polish Academy of Sciences: Technical Sciences

“…This process is directly associated with a function decomposition [14,22]. There is a range of academic tools that allow for function decomposition [5,11,21,26,27]; there are also many well known models of decomposition [4,11,17,25]. Particularly popular models include AIG partitioning [3,9,19,20,23] and methods using cutting of BDD diagrams [13,15].…”

Lookup Table Merging for FPGA Technology Mapping

“…Existing tools use technology mapping to generate single-output LUT and then combine the singleoutput LUTs into dual-output LUTs. Although the previous work has done some optimizations on the merging of dual-output LUTs, such as WireMap [8] using the heuristic algorithm of edge recovery to increase the LUT merging rate. Machado et al [9] used KL-cuts for multi-output mapping, but the merging efficiency is still low.…”