Factor cuts

Abstract

Enumeration of bounded size cuts is an important step in several logic synthesis algorithms such as technology mapping and re-writing. The standard algorithm does not scale beyond 6 or 7 inputs because it enumerates all cuts and there are too many of them. We address the enumeration problem by introducing the notion of cut factorization. In cut factorization, one enumerates global and local cuts (collectively called the factor cuts) of the network, and uses these to generate other cuts. Depending on how global and local cuts are defined, one obtains different factorization schemes. In the first scheme, complete factorization, it is possible to generate any cut from factor cuts. However, complete factorization is expensive though less expensive than exhaustive enumeration. In the second scheme, partial factorization, there is no guarantee of generating all cuts from factor cuts. However, it is much faster, and produces good results. In this paper we also present two applications of factor cuts: LUT mapping and macrocell mapping. In LUT mapping, we find that considering only factor cuts guarantees depth optimality for most nodes in the network. For the remaining nodes, other cuts need to be generated from factor cuts and examined. In macrocell mapping, we focus on a particular 9-input macrocell, and use factor cuts as a heuristic method to improve depth by reducing structural bias. Factor cuts are used to map the macrocell as a whole whenever possible instead of mapping its parts separately. In this context factor cuts enable a new quality-run-time tradeoff between mapping parts of the macrocell separately (poor quality), and mapping using all 9-input cuts (long run-time).

Scalable Synthesis and Clustering Techniques Using Decision Diagrams

“…The primary benefit of our approach is its generality. For example, there has been extensive research done on pruning the solution space of cut generation to reduce its runtime and memory use [9], [12]. Interestingly, all these techniques are orthogonal to our work.…”

“…Problem Description and Related Work 1) Cut Generation: While cut generation has been traditionally applied to iterative FPGA technology mappers, such as DAOmap [10] and IMap [11], there has been a renewed interest in the cut generation problem [3], [12] due to its growing use in several other CAD problems including:…”

Boolean Decomposition for AIG Optimization

“…Let ΦK (n) to be the set of K-cuts of n ∈ G and, if n is an AND node, let n1 and n2 to be its inputs. Then, ΦK (n) is defined recursively [4], as described in (4).…”

“…Algorithms based on K-cut enumeration have been proposed, such as factor cuts [4] and priority cuts [14], reducing the search space and enabling cuts with more nodes and inputs. Also, multi-output blocks based on K-cuts were presented [8,9], which extract the complete local context.…”

Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates

“…There are extensive studies (e.g., [12,13,14,15,16,17]) on synthesis for homogeneous PLBs, but only limited research on synthesis for heterogeneous PLBs. [10] proposed heuristics to speedup the technology mapping for homogeneous PLBs and then extended them to consider heterogeneous PLBs with mixed LUT sizes.…”