Reducing power dissipation in memory repair for high defect densities

Papavramidou, Panagiota; Nicolaidis, M.

doi:10.1109/ets.2013.6569372

Cited by 8 publications

(14 citation statements)

References 15 publications

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“…To cope with these issues, we use the following CAM repair scheme [10][12]- [14]. Each tag field of the run-time CAM and of the diagnosis CAM comprise a flag bit (repairflag) used for repair purposes.…”

Section: Transparent Bist For Srdf Test Algorithmsmentioning

confidence: 99%

“…Its power dissipation is also drastically reduced, but is still no negligible. Thus, as reported in the introduction, a new word repair architecture is introduced in [14] that drastically reduces this power. Diagnosis for ECC-based repair may also require a large diagnosis CAM [12], which will induce large area penalty and also large power dissipation during the test session.…”

mentioning

confidence: 97%

“…The present work, together with recent developments on ECC-based repair [12]- [14], are developed in the context of Cells framework [24]- [26]. This framework supports the design of massively parallel tera-device processors affected by high defect densities.…”

mentioning

confidence: 98%

“…These developments provide a comprehensive framework enabling low cost memory repair for high defect densities. For instance, for a 10 -3 defect density (1 faulty cell for every 1000 memory cells), conventional repair induces a 280% power penalty, while the combination of ECC-based repair with the power reduction architecture [14] induces a power penalty of only 8.8%.…”

mentioning

confidence: 99%

“…In another publication [13] an iterative diagnosis scheme is proposed for trading test length with area cost. In [14], a new word-repair architecture is proposed, which reduces drastically power dissipation for both ECCbased repair and conventional repair. These developments provide a comprehensive framework enabling low cost memory repair for high defect densities.…”

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confidence: 99%

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Transparent BIST for ECC-based memory repair

Nicolaidis

Papavramidou

2013

2013 IEEE 19th International on-Line Testing Symposium (IOLTS)

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International audienceEmbedded memories occupy the largest part of modern SoCs and include an even larger amount of transistors. As memories are designed very tightly to the technology limits, they are more prone to failures than other circuits. Thus, they concentrate the large majority of fabrication defects affecting yield adversely. Defect densities are expected to sharply increase in ultimate CMOS and post CMOS processes, resulting in high defect densities. These problems will further worsen due to stringent low-power constraints requiring drastic reduction of voltage levels. To cope with the resulting high defect densities in cost effective manner, ECC-based repair combining ECC with spare words becomes mandatory. On the other hand, coping with accelerating aging may require testing the memories during application execution, making mandatory transparent BIST Nevertheless, traditional implementations of transparent BIST do not comply with the constraints of ECC-based repair. To cope with this issue the paper proposes a transparent BIST architecture compliant with ECC-based repair

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Section: Transparent Bist For Srdf Test Algorithmsmentioning

confidence: 99%

mentioning

confidence: 97%

mentioning

confidence: 98%

mentioning

confidence: 99%

mentioning

confidence: 99%

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Transparent BIST for ECC-based memory repair

Nicolaidis

Papavramidou

2013

2013 IEEE 19th International on-Line Testing Symposium (IOLTS)

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Defending cache memory against cold-boot attacks boosted by power or EM radiation analysis

Neagu

Manich

2017

Microelectronics Journal

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Some algorithms running with compromised data select cache memory as a type of secure memory where data is confined and not transferred to main memory. However, cold-boot attacks that target cache memories exploit the data remanence. Thus, a sudden power shutdown may not delete data entirely, giving the opportunity to steal data. The biggest challenge for any technique aiming to secure the cache memory is performance penalty. Techniques based on data scrambling have demonstrated that security can be improved with a limited reduction in performance. However, they still cannot resist side-channel attacks like power or electromagnetic analysis. This paper presents a review of known attacks on memories and countermeasures proposed so far and an improved scrambling technique named random masking interleaved scrambling technique (RM-ISTe). This method is designed to protect the cache memory against cold-boot attacks, even if these are boosted by side-channel techniques like power or electromagnetic analysis.Postprint (author's final draft

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Low-power memory repair for high defect densities

Papavramidou

Nicolaidis

2015

2015 IEEE 21st International on-Line Testing Symposium (IOLTS)

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We illustrate that memory repair for high fault rates can be exploited for improving yield, extending lifetime, reducing power, and improving reliability, and consequently can be used to push aggressively the limits of technology scaling. We also present recent advances in low-area and low-power memory repair for high fault rates. As one of our main goals is to use this repair for reducing as much as possible the power dissipation of the memory system, the power dissipation of the repair circuitry should be kept as low as possible. To comply with this constraint, we also propose a repair approach, which further reduces the power dissipation of the repair circuit.

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Reducing power dissipation in memory repair for high defect densities

Cited by 8 publications

References 15 publications

Transparent BIST for ECC-based memory repair

Transparent BIST for ECC-based memory repair

Defending cache memory against cold-boot attacks boosted by power or EM radiation analysis

Low-power memory repair for high defect densities

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