Transparent BIST for ECC-based memory repair

Abstract

International audienceEmbedded memories occupy the largest part of modern SoCs and include an even larger amount of transistors. As memories are designed very tightly to the technology limits, they are more prone to failures than other circuits. Thus, they concentrate the large majority of fabrication defects affecting yield adversely. Defect densities are expected to sharply increase in ultimate CMOS and post CMOS processes, resulting in high defect densities. These problems will further worsen due to stringent low-power constraints requiring drastic reduction of voltage levels. To cope with the resulting high defect densities in cost effective manner, ECC-based repair combining ECC with spare words becomes mandatory. On the other hand, coping with accelerating aging may require testing the memories during application execution, making mandatory transparent BIST Nevertheless, traditional implementations of transparent BIST do not comply with the constraints of ECC-based repair. To cope with this issue the paper proposes a transparent BIST architecture compliant with ECC-based repair

Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair

“…The ECC-based memory architecture is based on work [5]. It is composed of memory, ECC circuit blocks, memory built-in self-test (BIST), diagnosis and remap content addressable memory (CAM) and remap controller (Fig.…”

“…b. Diagnosis CAM: A diagnosis CAM is adapted [5] to classify faulty words based on the number of faulty bits. It stores the address of the faulty word, and the faulty bit locations within the word, once a faulty bit is detected during test.…”

“…The scrubbing interval t s is set to occur every 6 minutes, while selftest and repair is set to occur every 10 days. The reliability of the proposed strategy is compared to the reliability of the traditional combined approach strategy [2], [5], where only uncorrectable words are repaired, while correctable words are left to the ECC.…”

“…This implies that power or latency over- head to access CAMs during test mode is negligible in early life, and it is slightly increased with time. These overheads can be reduced by dividing a whole memory into blocks and applying the test and repair to each memory block [5].…”

“…The work [2] enhances yield by allowing correctable words to be shipped since ECC will be able to handle them during system use. The work [5] improves reliability by performing in-field self-repair only to uncorrectable words, letting ECC handle correctable words, and preserving remaining spare elements for future uncorrectable words. However, in both works, since correctable words are used by the system, memory words are always susceptible to occurrences of additional errors, which leads to occurrence of uncorrectable words, and thus, leads to memory failure.…”