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SUMMARYThis study considers a set of n rectangles arranged on a plane, and, in particular, the problem of modifying the initial layout within a minimum area while meeting certain conditions, namely, preservation of orthogonal order and prevention of intersection between rectangles. A heuristic algorithm for this problem with O(n 2 ) complexity was proposed by Misue and colleagues. First, the problem of minimum-area layout adjustment is shown to be NP-complete. Then, another heuristic algorithm is examined that results in smaller layout area than that of Misue and colleagues. Using computational experiments with random initial layouts, the proposed algorithm is proven to require 15 to 20% of the area required by the Misue algorithm, especially with a large number of rectangles.

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This paper presents a novel failure prediction technique that is applicable for system-on-chips (SoCs). Highly reliable systems such as automobiles, aircrafts, or medical equipments would not allow any interruptive erroneous responses during system operations, which might result in catastrophes. Therefore, we propose a failure prediction technique that can be applied during an idle time when a system is not working, such as power-on/-off time. To achieve high reliability in the field, the proposed technique should take into consideration various types of aging mechanisms and the testing environment of voltage and temperature which is uncontrollable in the field. Therefore, we propose: 1) an accurate delay measurement technique considering the variation due to voltage and temperature and 2) an adaptive test scheduling that gives more test chances to more probable degrading parts. Experimental results show the required memory space and area cost for implementing the proposed technique.

Strabismic preterm SD children are at high risk for visual dysfunction. Constructional dyspraxia was frequently found in SD children and may be a dysfunction isolated from ophthalmological and visual perceptual dysfunctions.

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In return for increased operating frequency and reduced supply voltage in nano-scale designs, their vulnerability to IR-drop-induced yield loss grew increasingly apparent. Therefore, it is necessary to consider delay increase effect due to IR-drop during at-speed scan testing. However, it consumes significant amounts of time for precise IR-drop analysis. This paper addresses this issue with a novel percell dynamic IR-drop estimation method. Instead of performing time-consuming IR-drop analysis for each pattern one by one, the proposed method uses global cycle average power profile for each pattern and dynamic IRdrop profiles for a few representative patterns, thus total computation time is effectively reduced. Experimental results on benchmark circuits demonstrate that the proposed method achieves both high accuracy and high time-efficiency.

We propose an algorithm for the gathering problem of mobile agents in arbitrary networks (graphs) with Byzantine agents. Our algorithm can make all correct agents meet at a single node in O(f m) time (f is the upper bound of the number of Byzantine agents and m is the number of edges) under the assumption that agents have unique ID and behave synchronously, each node is equipped with an authenticated whiteboard, and f is known to agents. Here, the whiteboard is a node memory where agents can leave information. Since the existing algorithm achieves gathering without a whiteboard inÕ(n 9 λ) time, where n is the number of nodes and λ is the length of the longest ID, our algorithm shows an authenticated whiteboard can significantly reduce the time for the gathering problem in Byzantine environments.