Reducing instruction bit-width for low-power VLIW architectures

Abstract

VLIW (very long instruction word) architectures have proven to be useful for embedded applications with abundant instruction level parallelism. But due to the long instruction bus width it often consumes more power and memory space than necessary. One way to lessen this problem is to adopt a reduced bit-width instruction set architecture (ISA) that has a narrower instruction word length. This facilitates a more efficient hardware implementation in terms of area and power by decreasing bus-bandwidth requirements and the power dissipation associated with instruction fetches. In practice, however, it is impossible to convert a given ISA fully into an equivalent reduced bit-width one because the narrow instruction word, due to bitwidth restrictions, can encode only a small subset of normal instructions in the original ISA. Consequently, existing processors provide narrow instructions in very limited cases along with severe restrictions on register accessibility. The objective of this work is to explore the possibility of complete conversion, as a case study, of an existing 32-bit VLIW ISA into a 16-bit one that supports effectively all 32-bit instructions. To this objective, we attempt to circumvent the bit-width restrictions by dynamically extending the effective instruction word length of the converted 16-bit operations. Further, we will show that our proposed ISA conversion can create a synergy effect with a VLES (variable length execution set) architecture that is adopted in most recent VLIW processors. According to our experiment, the code size becomes significantly smaller after the conversion to 16-bit VLIW code. Also at a slight run time cost, the machine with the 16-bit ISA consumes much less energy than the original machine.

Improving performance of loops on DIAM-based VLIW architectures

“…Experimental results in [19] attest that the execution time increase can be up to 40%, and 10% on average, for the same set of kernels. Therefore to make the DIAM-based VLIW architecture more practical, the performance overhead must be minimized.…”

“…Once all partial instructions in the VLIW packet are combined with proper remote operands during the decode stage, every instruction in the packet becomes a complete instruction, ready for execution. Note that the above-mentioned decoding process for a single VLIW packet is finished within the timing bugdet of the decode stage(s) with the support of special hardware, as explained in [19]. Figure 4 shows an example of converting VLIW code in a 32-bit ISA into that of a 16-bit ISA for a DIAM-based VLIW proces- sor.…”

“…In our experiments, we have selected as the baseline configuration the 16-bit ISA 4-way DIAM-based VLIW processor, which was proposed and evaluated in the previous work [19]. The ISA of the baseline processor follows a typical RISC-style such as MIPS ISA [31].…”

“…To address these issues, Lee et al [19] have proposed a VLIW architecture with a reduced bit-width instruction set, where each instruction of a VLIW packet can have a 16-bit representation in addition to the original 32-bit format. Normally a reduced bit-width instruction set contains only a small subset of the original instruction set due to the reduced encoding space.…”

“…However, using Dynamic Implied Addressing Mode (DIAM) [37] excessive information that cannot be encoded within the reduced bit-width, such as a register number or an immediate value, can be specified as a separate instruction, and at runtime dynamically combined with the matching instruction. This hardware-assisted approach allows for 100% equivalent behavior as the original instruction sequence, while providing important benefits such as code size reduction (41% on average) and reduced energy consumption (8 ∼ 16% on average) on a 4-way VLIW processor for a set of compute-intensive kernels [19].…”