Compiler Optimization for Reducing Leakage Power in Multithread BSP Programs

Shih, Wen-Li; You, Yi-Ping; Huang, Chung-Wen; Lee, Jenq Kuen

doi:10.1145/2668119

Cited by 7 publications

(3 citation statements)

References 47 publications

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“…We demonstrate in Section 5.1.2 that for these use cases, SRA can provide sufficiently accurate information for design space exploration. More advanced concurrency analysis techniques, such as the ones employed in [29], could be combined with our techniques to scale our analysis to more complex concurrency patterns.…”

Section: Analysis Of Multi-threaded Programsmentioning

confidence: 99%

Energy Transparency for Deeply Embedded Programs

Georgiou

Kerrison

Chamski³

et al. 2017

ACM Trans. Archit. Code Optim.

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Energy transparency is a concept that makes a program's energy consumption visible, from hardware up to software, through the different system layers. Such transparency can enable energy optimizations at each layer and between layers, and help both programmers and operating systems make energy-aware decisions. In this paper, we focus on deeply embedded devices, typically used for Internet of Things (IoT) applications, and demonstrate how to enable energy transparency through existing Static Resource Analysis (SRA) techniques and a new target-agnostic profiling technique, without hardware energy measurements. Our novel mapping technique enables software energy consumption estimations at a higher level than the Instruction Set Architecture (ISA), namely the LLVM Intermediate Representation (IR) level, and therefore introduces energy transparency directly to the LLVM optimizer. We apply our energy estimation techniques to a comprehensive set of benchmarks, including single- and also multi-threaded embedded programs from two commonly used concurrency patterns, task farms and pipelines. Using SRA, our LLVM IR results demonstrate a high accuracy with a deviation in the range of 1% from the ISA SRA. Our profiling technique captures the actual energy consumption at the LLVM IR level with an average error of 3%.Comment: 33 pages, 7 figures. arXiv admin note: substantial text overlap with arXiv:1510.0709

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Section: Analysis Of Multi-threaded Programsmentioning

confidence: 99%

Energy Transparency for Deeply Embedded Programs

Georgiou

Kerrison

Chamski³

et al. 2017

ACM Trans. Archit. Code Optim.

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“…Chen et al [8] introduced a graph-based interleaving algorithm with a context-insensitive thread model. Shin et al [40] presents a power-gating analysis framework (MTPG) for multithreaded programs. MTPG analyzes MHP information among threads to report the component usages shared by multiple threads in hierarchical BSP models.…”

Section: Interleaving Analysis For Multithreaded Programsmentioning

confidence: 99%

Accelerating Dynamic Data Race Detection Using Static Thread Interference Analysis

Peng

Sui

2016

Proceedings of the 7th International Workshop on Programming Models and Applications for Multicores and Manycores

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Precise dynamic race detectors report an error if and only if more than one thread concurrently exhibits conflict on a memory access. They insert instrumentations at compiletime to perform runtime checks on all memory accesses to ensure that all races are captured and no spurious warnings are generated. However, a dynamic race check for a particular memory access statement is guaranteed to be redundant if the statement can be statically identified as thread interference-free. Despite significant recent advances in dynamic detection techniques, the redundant check remains a critical factor that leads to prohibitive overhead of dynamic race detection for multithreaded programs.In this paper, we present a new framework that eliminates redundant race check and boosts the dynamic race detection by performing static optimizations on top of a series of thread interference analysis phases. Our framework is implemented on top of LLVM 3.5.0 and evaluated with an industry dynamic race detector TSAN which is available as a part of LLVM tool chain. 11 benchmarks from SPLASH2 are used to evaluate the effectiveness of our approach in accelerating TSAN by eliminating redundant interference-free checks. The experimental result demonstrates our new approach achieves from 1.4x to 4.0x (2.4x on average) speedup over original TSAN under 4 threads setting, and achieves from 1.3x to 4.6x (2.6x on average) speedup under 16 threads setting.

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“…Therefore, hardware supports are essential in providing power gating controller and gating circuits of the functional units. According to the theoretical analysis and preliminary experimental results in [19], such a approach could be a solution for multicore application with BSP pattern.…”

Section: Bulk Synchronous Parallel Modelmentioning

confidence: 99%

Compilers for Low Power with Design Patterns on Embedded Multicore Systems

Lin

Kuan

Shih

et al. 2014

J Sign Process Syst

Self Cite

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Minimization of power dissipation can be considered at algorithmic, compiler, architectural, logic, and circuit level. Recent research trends for multicore programming models have come to the direction that parallel design patterns can be a solution to develop multicore applications. As parallel design patterns are with regularity, we view this as a great opportunity to exploit power optimizations in the software layer. In this paper, we investigate compilers for low power with parallel design patterns on embedded multicore systems. We evaluate four major parallel design patterns, Pipe and Filter, MapReduce with Iterator, Puppeteer, and Bulk Synchronous Parallel (BSP) Model. Our work attempts to devise power optimization schemes in compilers by exploiting the opportunities of the recurring patterns of embedded multicore programs. The proposed optimization schemes are rate-based optimization for Pipe and Filter pattern , early-exit power optimization for MapReduce with Iterator pattern, power aware mapping algorithm for Puppeteer pattern, and multi-phases power gating scheme for BSP pattern. In our experiments, real world multicore applications are evaluated on a multicore power simulator. Significant power reductions are observed from the experimental results. Therefore, we present a direction for power optimizations that one can further

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Compiler Optimization for Reducing Leakage Power in Multithread BSP Programs

Cited by 7 publications

References 47 publications

Energy Transparency for Deeply Embedded Programs

Energy Transparency for Deeply Embedded Programs

Accelerating Dynamic Data Race Detection Using Static Thread Interference Analysis

Compilers for Low Power with Design Patterns on Embedded Multicore Systems

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