Compilers for Low Power with Design Patterns on Embedded Multicore Systems

Lin, Cheng-Yen; Kuan, Chung‐Ming; Shih, Wen-Li; Lee, Jenq Kuen

doi:10.1007/s11265-014-0917-9

Cited by 3 publications

(2 citation statements)

References 28 publications

(27 reference statements)

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“…The dynamic task mapping approach necessitates a fast and low overhead pattern detection technique. Parallel patterns have been used to devise power optimization schemes in compilers by exploiting the opportunities of the recurring patterns of embedded multicore programs [37]. The authors validate their technique for low power with parallel design patterns on FIR and image recognition applications and they observe significant power reduction.…”

Section: Motivation For Classifying Parallel Patternsmentioning

confidence: 90%

Using Machine Learning Techniques to Detect Parallel Patterns of Multi-threaded Applications

Deniz

Şen

2015

Int J Parallel Prog

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Multicore hardware and software are becoming increasingly more complex. The programmability problem of multicore software has led to the use of parallel patterns. Parallel patterns reduce the effort and time required to develop multicore software by effectively capturing its thread communication and data sharing characteristics. Hence, detecting the parallel pattern used in a multi-threaded application is crucial for performance improvements and enables many architectural optimizations; however, this topic has not been widely studied. We apply machine learning techniques in a novel approach to automatically detect parallel patterns and compare these techniques in terms of accuracy and speed. We experimentally validate the detection ability of our techniques on benchmarks including PARSEC and Rodinia. Our experiments show that the k-nearest neighbor, decision trees, and naive Bayes classifier are the most accurate techniques. Overall, decision trees are the fastest technique with the lowest characterization overhead producing the best combination of detection results. We also show the usefulness of the proposed techniques on synthetic benchmark generation.

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Section: Motivation For Classifying Parallel Patternsmentioning

confidence: 90%

Using Machine Learning Techniques to Detect Parallel Patterns of Multi-threaded Applications

Deniz

Şen

2015

Int J Parallel Prog

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“…The power-aware flow graphs can then be used to identify code regions where several of the processor's functional units can be turned off during execution to reduce the static power dissipation. [70] demonstrate a framework that enables the compiler to support a number of energy-related optimizations for parallel design patterns. A series of pragmas were introduced to identify specific parallel design patterns and guide the compiler to apply power optimizations.…”

Section: Related Workmentioning

confidence: 99%

Energy Transparency for Deeply Embedded Programs

Georgiou

Kerrison

Chamski³

et al. 2017

ACM Trans. Archit. Code Optim.

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Energy transparency is a concept that makes a program's energy consumption visible, from hardware up to software, through the different system layers. Such transparency can enable energy optimizations at each layer and between layers, and help both programmers and operating systems make energy-aware decisions. In this paper, we focus on deeply embedded devices, typically used for Internet of Things (IoT) applications, and demonstrate how to enable energy transparency through existing Static Resource Analysis (SRA) techniques and a new target-agnostic profiling technique, without hardware energy measurements. Our novel mapping technique enables software energy consumption estimations at a higher level than the Instruction Set Architecture (ISA), namely the LLVM Intermediate Representation (IR) level, and therefore introduces energy transparency directly to the LLVM optimizer. We apply our energy estimation techniques to a comprehensive set of benchmarks, including single- and also multi-threaded embedded programs from two commonly used concurrency patterns, task farms and pipelines. Using SRA, our LLVM IR results demonstrate a high accuracy with a deviation in the range of 1% from the ISA SRA. Our profiling technique captures the actual energy consumption at the LLVM IR level with an average error of 3%.Comment: 33 pages, 7 figures. arXiv admin note: substantial text overlap with arXiv:1510.0709

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A Compilation Tool for Computation Offloading in ReRAM-based CIM Architectures

Jin,

Lei,

Liu

et al. 2023

ACM Trans. Archit. Code Optim.

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Computing-In-Memory (CIM) architectures using Non-Volatile Memories (NVMs) have emerged as a promising way to address the “memory wall” problem in traditional Von Neumann architectures. CIM accelerators can perform arithmetic or Boolean logic operations in NVMs by fully exploiting their high parallelism for bit-wise operations. These accelerators are often used in cooperation with general-purpose processors to speed up a wide variety of artificial neural network applications. In such a heterogeneous computing architecture, the legacy software should be redesigned and re-engineered to utilize new CIM accelerators. In this paper, we propose a compilation tool to automatically migrate legacy programs to such heterogeneous architectures based on the LLVM compiler infrastructure. To accelerate some computations such as vector-matrix multiplication in CIM accelerators, we identify several typical computing patterns from LLVM intermediate representations (IRs), which are oblivious to high-level programming paradigms. Our compilation tool can modify acceleratable LLVM IRs to offload them to CIM accelerators automatically, without re-engineering legacy software. Experimental results show that our compilation tool can translate many legacy programs to CIM-supported binary executables effectively, and improve application performance and energy efficiency by up to 51 × and 309 ×, respectively, compared with general-purpose x86 processors.

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Compilers for Low Power with Design Patterns on Embedded Multicore Systems

Cited by 3 publications

References 28 publications

Using Machine Learning Techniques to Detect Parallel Patterns of Multi-threaded Applications

Using Machine Learning Techniques to Detect Parallel Patterns of Multi-threaded Applications

Energy Transparency for Deeply Embedded Programs

A Compilation Tool for Computation Offloading in ReRAM-based CIM Architectures

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