VLIW (very long instruction word) architectures have proven to be useful for embedded applications with abundant instruction level parallelism. But due to the long instruction bus width it often consumes more power and memory space than necessary. One way to lessen this problem is to adopt a reduced bit-width instruction set architecture (ISA) that has a narrower instruction word length. This facilitates a more efficient hardware implementation in terms of area and power by decreasing bus-bandwidth requirements and the power dissipation associated with instruction fetches. In practice, however, it is impossible to convert a given ISA fully into an equivalent reduced bit-width one because the narrow instruction word, due to bitwidth restrictions, can encode only a small subset of normal instructions in the original ISA. Consequently, existing processors provide narrow instructions in very limited cases along with severe restrictions on register accessibility. The objective of this work is to explore the possibility of complete conversion, as a case study, of an existing 32-bit VLIW ISA into a 16-bit one that supports effectively all 32-bit instructions. To this objective, we attempt to circumvent the bit-width restrictions by dynamically extending the effective instruction word length of the converted 16-bit operations. Further, we will show that our proposed ISA conversion can create a synergy effect with a VLES (variable length execution set) architecture that is adopted in most recent VLIW processors. According to our experiment, the code size becomes significantly smaller after the conversion to 16-bit VLIW code. Also at a slight run time cost, the machine with the 16-bit ISA consumes much less energy than the original machine.
A compound instruction, encoding several ALU or memory operations within an instruction word, has been regarded as an efficient way of improving performance. In the compiler for embedded processors, the code generation algorithm for compound instructions has been built by dealing mainly with instruction selection which is a crucial phase of code generation. In this paper, we propose an iterative code generation algorithm for minimizing the detrimental impact of register coalescing that is applied to the code with compound instructions generated earlier from the instruction selection phase.
Various sensor nodes used in IoT network systems composed of electronic devices perform various control tasks using the results measured by the sensors. At this point, if these sensing tasks are smartly assigned and performed, the energy consuming efficiency of the entire networked system can be improved. That is, since each sensor node constituting the IoT network system performs redundant sensing and control devices, it is possible to improve the network’s energy efficiency by appropriately assigning and removing such redundant sensing tasks. In particular, the indoor illuminance sensor is installed in various devices such as automatic light switch systems, smart phones, and tablets. It is desirable that only one sensor node among them participates in the actual sensing task. In a smart home, redundant sensors and controllers are used repeatedly in refrigerators, heaters, TVs, artificial intelligence speakers, ventilation facilities, and smartphones. These redundant sensing and control signal generation lowers energy consumption’s efficiency. This study proposes a technique that can properly eliminate unnecessary and redundant sensing tasks that occur when such on the flown IoT network system is built. As a result, it has been shown that the efficiency of energy consumption can be improved in the entire IoT sensor network system.
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