Reducing hardware requirement in FIR filter design

Soderstrand, M.A.; Johnson, L.G.; Arichanthiran, H.; Hoque, M.D.; Elangovan, R.

doi:10.1109/icassp.2000.860099

Cited by 16 publications

(8 citation statements)

References 25 publications

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“…To reduce the number of operators, first use a CSE algorithm with a based on the canonical signed digit (CSD) representation of filter coefficients for implementing low complexity FIR filters [4]. In CSDs, it is difficult to deal with "+" and "−" [5].…”

Section: Common Sub-expression Elimination (Cse) Techniquementioning

confidence: 99%

“…Soderstrand et al [4] proposed a hardware optimization technique based on minimum adder CSD multiplier blocks is combined with a technique for trading adders to reduce hardware requirements for FIR filter coefficients. Noise free filters can only be achieved using FIR filters because FIR filters can always designed using a sufficient number of bits in the multipliers that rounding or truncation after multiple is not necessary.…”

Section: Literature Surveymentioning

confidence: 99%

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Efficient Finite Impulse Response Filter Architecture Using Multiple Constant Multiplication and Common Sub-Expression Elimination Techniques

Shukla

Beulet

2017

Asian J Pharm Clin Res

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Objective: This paper introduces the computationally efficient, low power, high speed partial reconfigurable Finite impulse response (FIR) filter design using multiple constant multiplication technique (MCM). The complexity of many digital signal processing (DSP) systems is reduced by multiple constant multiplication operation.Methods: Multiple constant multiplications (MCM) along with methods like common sub expression elimination (CSE) is used for the better performance of digital signal processing systems. This paper introduces a CSE operation of finite Impulse response filter design which is solved with decreased number of operators.Results: Using these techniques shows that the area efficiency is increased when compared with designs based on direct form implementation of FIR filters. Conclusion:This method has achieved minimum area and delay with a high process rate. The future work will be for using CSE for 0-1 ILP.

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Section: Common Sub-expression Elimination (Cse) Techniquementioning

confidence: 99%

Section: Literature Surveymentioning

confidence: 99%

Efficient Finite Impulse Response Filter Architecture Using Multiple Constant Multiplication and Common Sub-Expression Elimination Techniques

Shukla

Beulet

2017

Asian J Pharm Clin Res

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“…The partial terms can be pre-computed and stored in LUTs. Yoo et al [4,5,6] observed that the requirement of memory/LUT capacity increases exponentially with the order of the filter, given that DA implementations need 2Kwords, K being the number of taps of the filter. This approach has another problem in changing the filter coefficients for changing its functional characteristic as then the LUT contents need to be recomputed before the memory is rewritten.…”

Section: Introductionmentioning

confidence: 99%

Area Efficient Reloadable FIR Filter based on NEw Distributed Arithmetic (NEDA)

Roy¹

2016

IJERT

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This paper describes the design and implementation of highly efficient circuit for the implementation of FIR filter in terms of power and area keeping the speed at per with the fully parallel DA. It is a multiplier-less FIR filter which is designed based on new distributed arithmetic algorithm (NEDA). This NEDA based technique consists of Multiplexers, shifters and accumulator. Moreover in this architecture the filter coefficients can be any time modified at once, which is certainly an advantage over simple DA where the LUT contents need to recomputed before the memory is rewritten. Analysis on the performance are done using Xilinx-Sysgen and Mathworks-Simulink. The proposed architecture provides an efficient implementation compared to other existing structures for FIR Filter.

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“…The SF steps through the range of SF-min to SF-mar with the step size of 2. ' , k 2 5 . We use scaling to improve our algorithm to allow a further reduction in nonzero bits is shown in the following section.…”

Section: B Scaling the Real Filtermentioning

confidence: 99%

“…As a result, the finite quantization wordlength behavior in a digital filter is extremely important [ l]- [5]. The consideration of finding good quantized coefficients attracts a great deal of attention.…”

Section: Introductionmentioning

confidence: 99%

An efficient design for FIR filters with variable precision

DeBrunner

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)

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We present an improved algorithm for selecting variable precision coefficients for FIR filters that produces a reduced space implementation with no degradation in frequency response. The algorithm is based on the fact that the frequency response of a filter has different sensitivities to different coefficients depending on the response itself (i.e. the coefficient value). The method provided here makes it possible to predict the variable precision of the quantized coefficients that are required to meet the specification. This approach, along with other technologies such as CSD and the scaling method used in our realizations, has opened exciting implementation possibilities for FPGAs, ASICs, and custom VLSI. The example study in this paper shows that using variable precision to exploit redundancy across the coefficients results in significant reductions in complexity and area over the uniform wordlength method.

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Reducing hardware requirement in FIR filter design

Cited by 16 publications

References 25 publications

Efficient Finite Impulse Response Filter Architecture Using Multiple Constant Multiplication and Common Sub-Expression Elimination Techniques

Efficient Finite Impulse Response Filter Architecture Using Multiple Constant Multiplication and Common Sub-Expression Elimination Techniques

Area Efficient Reloadable FIR Filter based on NEw Distributed Arithmetic (NEDA)

An efficient design for FIR filters with variable precision

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