Area Efficient Reloadable FIR Filter based on NEw Distributed Arithmetic (NEDA)

Abstract

This paper describes the design and implementation of highly efficient circuit for the implementation of FIR filter in terms of power and area keeping the speed at per with the fully parallel DA. It is a multiplier-less FIR filter which is designed based on new distributed arithmetic algorithm (NEDA). This NEDA based technique consists of Multiplexers, shifters and accumulator. Moreover in this architecture the filter coefficients can be any time modified at once, which is certainly an advantage over simple DA where the LUT contents need to recomputed before the memory is rewritten. Analysis on the performance are done using Xilinx-Sysgen and Mathworks-Simulink. The proposed architecture provides an efficient implementation compared to other existing structures for FIR Filter.

Power Optimized VLSI Architecture of Distributed Arithmetic Based Block LMS Adaptive Filter

“…Even though the sampling rate of the MAC is slower as compared to the LUT-based DA architectures as proposed in [11][12][13] it is only enabled whenever it is required by a slow rate clock which significantly reduces the power consumption of the Website: www.ijeer.forexjournal.co.in Power Optimized VLSI Architecture of Distributed Arithmetic Pressure Estimation with Photoplethysmography Signals and Semi-Classical Signal Analysis device. Another approach was presented in [14][15][16][17] which involved using Carry save accumulation (CSA) with a highfrequency clock instead of a MAC unit and used a slower clock for the other modules for power reduction. This asynchronous clocking system can lead to clock skew and besides, the device would also use extra power to operate two clocks one of them being a high-frequency clock.…”