Reducing energy consumption of video memory by bit-width compression

Moshnyaga, Vasily G.; Inoue, Katsuro; Fukagawa, Mizuka

doi:10.1145/566408.566446

Cited by 2 publications

(2 citation statements)

References 14 publications

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“…An important point to note is that these approximate circuits are hardwired and cannot be modified without resynthesizing the entire circuit. There also exist instances of approximations introduced in an MPEG encoder [5], [11]- [13]. Most of them exploit the inherent error resilience of the motion estimation (ME) algorithm, which results in minor quality degradation.…”

Section: Related Workmentioning

confidence: 99%

“…Most of them exploit the inherent error resilience of the motion estimation (ME) algorithm, which results in minor quality degradation. For example, Moshnyaga et al [11] use a bitwidth compression technique to reduce power consumption of video frame memory. He and Liou [12] and He et al [13] use bit truncation to introduce approximations in the ME block of an MPEG encoder.…”

Section: Related Workmentioning

confidence: 99%

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Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

Raha

Jayakumar

Raghunathan

2016

IEEE Trans. VLSI Syst.

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The field of approximate computing has received significant attention from the research community in the past few years, especially in the context of various signal processing applications. Image and video compression algorithms, such as JPEG, MPEG, and so on, are particularly attractive candidates for approximate computing, since they are tolerant of computing imprecision due to human imperceptibility, which can be exploited to realize highly power-efficient implementations of these algorithms. However, existing approximate architectures typically fix the level of hardware approximation statically and are not adaptive to input data. For example, if a fixed approximate hardware configuration is used for an MPEG encoder (i.e., a fixed level of approximation), the output quality varies greatly for different input videos. This paper addresses this issue by proposing a reconfigurable approximate architecture for MPEG encoders that optimizes power consumption with the goal of maintaining a particular Peak Signal-to-Noise Ratio (PSNR) threshold for any video. Toward this end, we design reconfigurable adder/subtractor blocks (RABs), which have the ability to modulate their degree of approximation, and subsequently integrate these blocks in the motion estimation and discrete cosine transform modules of the MPEG encoder. We propose two heuristics for automatically tuning the approximation degree of the RABs in these two modules during runtime based on the characteristics of each individual video. Experimental results show that our approach of dynamically adjusting the degree of hardware approximation based on the input video respects the given quality bound (PSNR degradation of 1%-10%) across different videos while achieving a power saving up to 38% over a conventional nonapproximated MPEG encoder architecture. Note that although the proposed reconfigurable approximate architecture is presented for the specific case of an MPEG encoder, it can be easily extended to other DSP applications.Index Terms-Approximate circuits, approximate computing, low power design, quality configurable.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

Raha

Jayakumar

Raghunathan

2016

IEEE Trans. VLSI Syst.

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Power- and Performance - Aware Architectures

Corretger¹

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The scaling of silicon technology has been ongoing for over forty years. We are on the way to commercializing devices having a minimum feature size of one-tenth of a micron. The push for miniaturization comes from the demand for higher functionality and higher performance at a lower cost. As a result, successively higher levels of integration have been driving up the power consumption of chips. Today, heat removal and power distribution are at the forefront of the problems faced by chip designers. In recent years portability has become important. Historically, portable applications were characterized by low throughput requirements such as for a wristwatch. This is no longer true. Among the new portable applications are hand-held multimedia terminals with video display and capture, audio reproduction and capture, voice recognition, and handwriting recognition capabilities. These capabilities call for a tremendous amount of computational capacity. This computational capacity has to be realized with very low power requirements in order for the battery to have a satisfactory life span. This thesis is an attempt to provide microarchitecture and compiler techniques for low-power chips with high-computational capacity. The first part of this work presents some schemes for reducing the complexity of the issue logic. The issue logic has become one of the main sources of energy consumption in recent years. The inherent associative look-up and the size of the structures (crucial for exploiting ILP), have led the issue logic to a significant energy budget. The techniques presented in this work eliminate or reduce the associative logic by determining producer-consumer relationships between the instructions or by scheduling the instructions according to the latency of the operations. An important effort has been deployed to reduce the energy requirements and the power dissipation through novel mechanisms based on value compression. As a result, the second part of this thesis introduces several ultra-low power and high-end processor designs. First, the design space for ultra-low power processors is explored. Several designs are developed (at the architectural level) from scratch that exploit value compression at all levels of the data-path. Second, value compression for high-performance processors is proposed and evaluated. At the end of this thesis, two compile-time techniques are presented that show how the compiler can help in reducing the energy consumption. By means of a static analysis of the program code or through profiling, the compiler is able to know the size of the operands involved in the computation. Through these analyses, the compiler is able to use narrower operations (i.e. a 64-bit addition can be converted to an 8-bit addition due to the information of the size of the operands). Overall, this thesis compromises the detailed study of one of the most power hungry units in a processor (the issue logic) and the use of value compression (through hardware and software) as a mean to reduce the energy consumption in all the stages of the pipeline.

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Reducing energy consumption of video memory by bit-width compression

Cited by 2 publications

References 14 publications

Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

Power- and Performance - Aware Architectures

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