Reducing Damage to Si Substrates during Gate Etching Processes

Abstract

The mechanism of formation of a “Si recess” that appears during gate poly-Si etching was studied. Hydrogen in HBr plasma penetrates through a thin gate oxide film and generates dislocated sites in the Si substrate. We developed a molecular dynamics (MD) simulation to clarify both the penetration depth of H and O and the dislocation of Si. The damage was successfully minimized by controlling the high energy peak in the ion energy distribution function (IEDF) to be lower than the threshold energy of ion penetration.

Simulation and experimental study on the characteristics of plasma-induced damage and methodology for accurate damage analysis

“…Total layer thickness (d SL + d IL ) saturated at approximately 5 nm. This is consistent with widely observed Si recess thickness [2]. d SL peaked at around E i ~ 50 eV and showed a turnover.…”

“…1) [1]. This damage is realized as "Si recess," which has been revealed to cause device performance degradation [2]. The depth of the damage is considered to be determined by plasma parameters, e.g., incident ion energy distribution function, electron temperature, and plasma density.…”

Effects of Plasma-Induced Si Recess Structure on n-MOSFET Performance Degradation

“…Physical damage [3], [6] is commonly associated with the damage induced by high-energy ion bombardment incident on Si or other material surfaces. The plasma-induced recess effect [7]- [10] is attributed to the physical damage during gate, offset spacer, and sidewall spacer etch processes. Removal of the damaged layer by a subsequent wet-stripping step results in the recess structure.…”

Application of Molecular Dynamics Simulations to Plasma Etch Damage in Advanced Metal-Oxide-Semiconductor Field-Effect Transistors

“…Since the damaged layer oxidizes due to an air exposure after the plasma etch, the portion is stripped off by the wet-etch. Then, the etched layer results in Si loss whose structure is observed as recessed Si surface, called "Si recess" (Ohchi et al, 2008;Petit-Etienne et al, 2010;Vitale & Smith, 2003). Si recess is formed in the source / drain extension (SDE) region in a MOSFET.…”