Effects of Plasma-Induced Si Recess Structure on n-MOSFET Performance Degradation

Abstract

Performance degradation of n-MOSFETs with plasma-induced recess structure was investigated. The depth of Si recess (d R ) was estimated from the experiments by using Ar gas plasmas. We propose an analytical model by assuming that the damage layer was formed during an offset spacer etch. A linear relationship between threshold voltage shift (ΔV th ) and d R was found. Device simulations were also performed for n-MOSFETs with various (d R ). Both |ΔV th | and OFF-state leakage current increased with an increase in d R . The increase in |ΔV th | becomes larger for smaller gate length. The results from device simulations are consistent with the analytical model. These findings imply that the Si recess structure induced by plasma damage enhances V th -variability in future devices.

Atomistic simulations of plasma process-induced Si substrate damage - Effects of substrate bias-power frequency

“…Plasma-induced physical damage (PPD) is induced by the bombardment of ions on Si substrate or other material surfaces. One of the typical PPD is Si loss in the source and drain extension region, called "Si recess" [1,2] that is observed in planar MOSFETs. Recently, several models [2,3]-damage layer creation, recess structure formation, and MOSFET degradation-have been proposed, where analytical predictions are available, and some of the models have been verified from experiments.…”

“…One of the typical PPD is Si loss in the source and drain extension region, called "Si recess" [1,2] that is observed in planar MOSFETs. Recently, several models [2,3]-damage layer creation, recess structure formation, and MOSFET degradation-have been proposed, where analytical predictions are available, and some of the models have been verified from experiments. This PPD not only degrades the MOSFET performance [2,4] but also enhances the parameter variations [5] in an LSI.…”

Alternative process for thin layer etching: Application to nitride spacer etching stopping on silicon germanium

“…For instance, an increase of the silicon recess as a function of the gate length (Lg) decrease leads to a threshold voltage decrease as well as an increase of the leakage current. 1 The problem is using conventional plasma etching, high energy ions are key in controlling etch anisotropy, but they also jeopardize the etch precision required when ultra-thin layers (few nanometers) are involved in the stack to pattern by transferring the reactive layer formed on the top of the etched film into the underlayer, damaging the film. 2,3 This leads to a material recess after wet cleaning.…”

Application of Molecular Dynamics Simulations to Plasma Etch Damage in Advanced Metal-Oxide-Semiconductor Field-Effect Transistors

“…As proposed by Eriguchi et al (Eriguchi et al, 2009a;Eriguchi et al, 2009b), Si recess depth d R and the local defect sites degrades MOSFET-operation parameters such as V th and I d , where I d is drain current determining the operation speed (Sze, 1981). These mechanisms are analytically expressed as,…”

“…It has been reported (Eriguchi et al, 2009a;Eriguchi et al, 2008a) that the Si recess structure by PID degrades MOSFET performance, i.e., induces the shift of threshold voltage (V th ) for MOSFET operation. Since V th (Sze, 1981;Sze & Ng, 2007) plays an important role in determining the performance, Si recess structure has become a primal problem in the present-day MOSFET development (SIA, 2009 structure (PID), the damage creation mechanism should be clarified from both theoretical and experimental viewpoints.…”